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Searched refs:EMC_DBG_WRITE_MUX_ACTIVE (Results 1 – 15 of 15) sorted by relevance

/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/memory/tegra/
H A Dtegra30-emc.c166 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) macro
674 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, in emc_prepare_timing_change()
700 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG); in emc_prepare_timing_change()
1075 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; in emc_setup_hw()
H A Dtegra20-emc.c99 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) macro
488 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; in emc_setup_hw()
H A Dtegra210-emc-cc-r21021.c1248 value = emc_dbg | (EMC_DBG_WRITE_MUX_ACTIVE | in tegra210_emc_r21021_set_clock()
1361 value = emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE | EMC_DBG_WRITE_ACTIVE_ONLY; in tegra210_emc_r21021_set_clock()
1603 ccfifo_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, in tegra210_emc_r21021_set_clock()
H A Dtegra210-emc.h24 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) macro
H A Dtegra210-emc-core.c889 emc_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()
891 emc_writel(emc, emc_dbg & ~EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/memory/tegra/
H A Dtegra30-emc.c166 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) macro
674 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, in emc_prepare_timing_change()
700 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG); in emc_prepare_timing_change()
1075 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; in emc_setup_hw()
H A Dtegra20-emc.c99 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) macro
488 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; in emc_setup_hw()
H A Dtegra210-emc-cc-r21021.c1248 value = emc_dbg | (EMC_DBG_WRITE_MUX_ACTIVE | in tegra210_emc_r21021_set_clock()
1361 value = emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE | EMC_DBG_WRITE_ACTIVE_ONLY; in tegra210_emc_r21021_set_clock()
1603 ccfifo_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, in tegra210_emc_r21021_set_clock()
H A Dtegra210-emc.h24 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) macro
H A Dtegra210-emc-core.c889 emc_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()
891 emc_writel(emc, emc_dbg & ~EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/memory/tegra/
H A Dtegra30-emc.c166 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) macro
674 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, in emc_prepare_timing_change()
700 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG); in emc_prepare_timing_change()
1075 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; in emc_setup_hw()
H A Dtegra20-emc.c99 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) macro
488 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; in emc_setup_hw()
H A Dtegra210-emc-cc-r21021.c1248 value = emc_dbg | (EMC_DBG_WRITE_MUX_ACTIVE | in tegra210_emc_r21021_set_clock()
1361 value = emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE | EMC_DBG_WRITE_ACTIVE_ONLY; in tegra210_emc_r21021_set_clock()
1603 ccfifo_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, in tegra210_emc_r21021_set_clock()
H A Dtegra210-emc.h24 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) macro
H A Dtegra210-emc-core.c889 emc_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()
891 emc_writel(emc, emc_dbg & ~EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()