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Searched refs:EMC_INTSTATUS (Results 1 – 18 of 18) sorted by relevance

/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/memory/tegra/
H A Dtegra20-emc.c32 #define EMC_INTSTATUS 0x000 macro
212 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
222 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
284 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
482 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
H A Dtegra30-emc.c36 #define EMC_INTSTATUS 0x000 macro
407 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
417 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
785 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
1069 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
H A Dtegra124-emc.c36 #define EMC_INTSTATUS 0x0 macro
565 value = readl(emc->regs + EMC_INTSTATUS); in emc_seq_wait_clkchange()
617 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
818 readl(emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
H A Dtegra210-emc.h21 #define EMC_INTSTATUS 0x0 macro
H A Dtegra210-emc-core.c844 emc_readl(emc, EMC_INTSTATUS); in tegra210_emc_do_clock_change()
848 err = tegra210_emc_wait_for_update(emc, 0, EMC_INTSTATUS, in tegra210_emc_do_clock_change()
H A Dtegra210-emc-cc-r21021.c750 emc_writel(emc, EMC_INTSTATUS_CLKCHANGE_COMPLETE, EMC_INTSTATUS); in tegra210_emc_r21021_set_clock()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/memory/tegra/
H A Dtegra20-emc.c32 #define EMC_INTSTATUS 0x000 macro
212 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
222 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
284 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
482 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
H A Dtegra30-emc.c36 #define EMC_INTSTATUS 0x000 macro
407 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
417 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
785 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
1069 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
H A Dtegra124-emc.c36 #define EMC_INTSTATUS 0x0 macro
565 value = readl(emc->regs + EMC_INTSTATUS); in emc_seq_wait_clkchange()
617 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
818 readl(emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
H A Dtegra210-emc.h21 #define EMC_INTSTATUS 0x0 macro
H A Dtegra210-emc-core.c844 emc_readl(emc, EMC_INTSTATUS); in tegra210_emc_do_clock_change()
848 err = tegra210_emc_wait_for_update(emc, 0, EMC_INTSTATUS, in tegra210_emc_do_clock_change()
H A Dtegra210-emc-cc-r21021.c750 emc_writel(emc, EMC_INTSTATUS_CLKCHANGE_COMPLETE, EMC_INTSTATUS); in tegra210_emc_r21021_set_clock()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/memory/tegra/
H A Dtegra20-emc.c32 #define EMC_INTSTATUS 0x000 macro
212 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
222 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
284 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
482 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
H A Dtegra30-emc.c36 #define EMC_INTSTATUS 0x000 macro
407 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
417 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
785 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
1069 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
H A Dtegra124-emc.c36 #define EMC_INTSTATUS 0x0 macro
565 value = readl(emc->regs + EMC_INTSTATUS); in emc_seq_wait_clkchange()
617 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
818 readl(emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
H A Dtegra210-emc.h21 #define EMC_INTSTATUS 0x0 macro
H A Dtegra210-emc-core.c844 emc_readl(emc, EMC_INTSTATUS); in tegra210_emc_do_clock_change()
848 err = tegra210_emc_wait_for_update(emc, 0, EMC_INTSTATUS, in tegra210_emc_do_clock_change()
H A Dtegra210-emc-cc-r21021.c750 emc_writel(emc, EMC_INTSTATUS_CLKCHANGE_COMPLETE, EMC_INTSTATUS); in tegra210_emc_r21021_set_clock()