| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/memory/tegra/ |
| H A D | tegra210-emc-cc-r21021.c | 994 emc_writel(emc, next->emc_mrw, EMC_MRW); in tegra210_emc_r21021_set_clock()
1078 emc_writel(emc, value, EMC_MRW); in tegra210_emc_r21021_set_clock()
1509 ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1543 EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1550 ccfifo_writel(emc, value, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
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| H A D | tegra30-emc.c | 83 #define EMC_MRW 0x0e8 macro
744 emc->regs + EMC_MRW); in emc_prepare_timing_change()
748 emc->regs + EMC_MRW); in emc_prepare_timing_change()
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| H A D | tegra124-emc.c | 110 #define EMC_MRW 0xe8 macro
795 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); in tegra_emc_prepare_timing_change()
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| H A D | tegra210-emc.h | 87 #define EMC_MRW 0xe8 macro
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/memory/tegra/ |
| H A D | tegra210-emc-cc-r21021.c | 994 emc_writel(emc, next->emc_mrw, EMC_MRW); in tegra210_emc_r21021_set_clock()
1078 emc_writel(emc, value, EMC_MRW); in tegra210_emc_r21021_set_clock()
1509 ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1543 EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1550 ccfifo_writel(emc, value, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
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| H A D | tegra30-emc.c | 83 #define EMC_MRW 0x0e8 macro
744 emc->regs + EMC_MRW); in emc_prepare_timing_change()
748 emc->regs + EMC_MRW); in emc_prepare_timing_change()
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| H A D | tegra124-emc.c | 110 #define EMC_MRW 0xe8 macro
795 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); in tegra_emc_prepare_timing_change()
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| H A D | tegra210-emc.h | 87 #define EMC_MRW 0xe8 macro
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/memory/tegra/ |
| H A D | tegra210-emc-cc-r21021.c | 994 emc_writel(emc, next->emc_mrw, EMC_MRW); in tegra210_emc_r21021_set_clock()
1078 emc_writel(emc, value, EMC_MRW); in tegra210_emc_r21021_set_clock()
1509 ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1543 EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1550 ccfifo_writel(emc, value, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
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| H A D | tegra30-emc.c | 83 #define EMC_MRW 0x0e8 macro
744 emc->regs + EMC_MRW); in emc_prepare_timing_change()
748 emc->regs + EMC_MRW); in emc_prepare_timing_change()
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| H A D | tegra124-emc.c | 110 #define EMC_MRW 0xe8 macro
795 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); in tegra_emc_prepare_timing_change()
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| H A D | tegra210-emc.h | 87 #define EMC_MRW 0xe8 macro
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/mach-tegra/ |
| H A D | sleep-tegra30.S | 23 #define EMC_MRW 0xe8 macro
548 str r2, [r0, #EMC_MRW]
558 str r2, [r0, #EMC_MRW]
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm/mach-tegra/ |
| H A D | sleep-tegra30.S | 23 #define EMC_MRW 0xe8 macro
548 str r2, [r0, #EMC_MRW]
558 str r2, [r0, #EMC_MRW]
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| /dports/multimedia/libv4l/linux-5.13-rc2/arch/arm/mach-tegra/ |
| H A D | sleep-tegra30.S | 23 #define EMC_MRW 0xe8 macro
548 str r2, [r0, #EMC_MRW]
558 str r2, [r0, #EMC_MRW]
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| /dports/multimedia/libv4l/linux-5.13-rc2/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nvidia,tegra124-emc.yaml | 118 value of the EMC_MRW register for this set of timings
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nvidia,tegra124-emc.yaml | 118 value of the EMC_MRW register for this set of timings
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nvidia,tegra124-emc.yaml | 118 value of the EMC_MRW register for this set of timings
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