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Searched refs:EMC_SELF_REF (Results 1 – 18 of 18) sorted by relevance

/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/mach-tegra/
H A Dsleep-tegra20.S26 #define EMC_SELF_REF 0xe0 macro
241 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
360 str r2, [r1, #EMC_SELF_REF]
H A Dsleep-tegra30.S22 #define EMC_SELF_REF 0xe0 macro
505 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
854 str r1, [r0, #EMC_SELF_REF]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm/mach-tegra/
H A Dsleep-tegra20.S26 #define EMC_SELF_REF 0xe0 macro
241 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
360 str r2, [r1, #EMC_SELF_REF]
H A Dsleep-tegra30.S22 #define EMC_SELF_REF 0xe0 macro
505 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
854 str r1, [r0, #EMC_SELF_REF]
/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm/mach-tegra/
H A Dsleep-tegra20.S26 #define EMC_SELF_REF 0xe0 macro
241 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
360 str r2, [r1, #EMC_SELF_REF]
H A Dsleep-tegra30.S22 #define EMC_SELF_REF 0xe0 macro
505 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
854 str r1, [r0, #EMC_SELF_REF]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c864 ccfifo_writel(emc, 1, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1264 ccfifo_writel(emc, 0x101, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1266 ccfifo_writel(emc, 0x1, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1440 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1463 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1476 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1499 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
H A Dtegra124-emc.c106 #define EMC_SELF_REF 0xe0 macro
760 EMC_SELF_REF); in tegra_emc_prepare_timing_change()
768 EMC_SELF_REF); in tegra_emc_prepare_timing_change()
H A Dtegra30-emc.c82 #define EMC_SELF_REF 0x0e0 macro
693 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
718 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
H A Dtegra210-emc.h86 #define EMC_SELF_REF 0xe0 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c864 ccfifo_writel(emc, 1, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1264 ccfifo_writel(emc, 0x101, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1266 ccfifo_writel(emc, 0x1, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1440 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1463 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1476 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1499 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
H A Dtegra124-emc.c106 #define EMC_SELF_REF 0xe0 macro
760 EMC_SELF_REF); in tegra_emc_prepare_timing_change()
768 EMC_SELF_REF); in tegra_emc_prepare_timing_change()
H A Dtegra30-emc.c82 #define EMC_SELF_REF 0x0e0 macro
693 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
718 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
H A Dtegra210-emc.h86 #define EMC_SELF_REF 0xe0 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c864 ccfifo_writel(emc, 1, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1264 ccfifo_writel(emc, 0x101, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1266 ccfifo_writel(emc, 0x1, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1440 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1463 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1476 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
1499 ccfifo_writel(emc, 0, EMC_SELF_REF, 0); in tegra210_emc_r21021_set_clock()
H A Dtegra124-emc.c106 #define EMC_SELF_REF 0xe0 macro
760 EMC_SELF_REF); in tegra_emc_prepare_timing_change()
768 EMC_SELF_REF); in tegra_emc_prepare_timing_change()
H A Dtegra30-emc.c82 #define EMC_SELF_REF 0x0e0 macro
693 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
718 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
H A Dtegra210-emc.h86 #define EMC_SELF_REF 0xe0 macro