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Searched refs:ENABLE_L1_TLB (Results 1 – 25 of 99) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v2_0.c193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
373 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_0_gart_disable()
H A Dgfxhub_v1_0.c159 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
361 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v1_0_gart_disable()
H A Dgfxhub_v2_1.c191 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
391 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_1_gart_disable()
H A Dmmhub_v2_0.c238 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
430 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_0_gart_disable()
H A Dmmhub_v2_3.c190 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_3_init_tlb_regs()
384 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_3_gart_disable()
H A Dmmhub_v1_0.c142 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
352 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v1_0_gart_disable()
H A Dgmc_v7_0.c631 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v7_0_gart_enable()
752 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v7_0_gart_disable()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c159 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
361 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v1_0_gart_disable()
H A Dgfxhub_v2_0.c193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
373 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_0_gart_disable()
H A Dgfxhub_v2_1.c191 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
391 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_1_gart_disable()
H A Dmmhub_v2_3.c190 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_3_init_tlb_regs()
384 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_3_gart_disable()
H A Dmmhub_v2_0.c238 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
430 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_0_gart_disable()
H A Dmmhub_v1_0.c142 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
352 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v1_0_gart_disable()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c159 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
361 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v1_0_gart_disable()
H A Dgfxhub_v2_0.c193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
373 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_0_gart_disable()
H A Dgfxhub_v2_1.c191 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
391 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_1_gart_disable()
H A Dmmhub_v2_0.c238 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
430 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_0_gart_disable()
H A Dmmhub_v2_3.c190 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_3_init_tlb_regs()
384 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_3_gart_disable()
H A Dmmhub_v1_0.c142 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
352 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v1_0_gart_disable()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.h406 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
606 type ENABLE_L1_TLB;\
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.h406 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
606 type ENABLE_L1_TLB;\
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.h406 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
606 type ENABLE_L1_TLB;\
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubp.c68 ENABLE_L1_TLB, 1, in hubp3_set_vm_system_aperture_settings()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubp.c68 ENABLE_L1_TLB, 1, in hubp3_set_vm_system_aperture_settings()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubp.c68 ENABLE_L1_TLB, 1, in hubp3_set_vm_system_aperture_settings()

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