/dports/devel/directfb/DirectFB-1.4.17/gfxdrivers/pxa3xx/ |
H A D | pxa3xx_regs.h | 72 #define FBR5 (PXA3XX_LCD_BASE + 0x0110) macro
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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/mach-pxa/include/mach/ |
H A D | regs-lcd.h | 27 #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ macro
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/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm/mach-pxa/include/mach/ |
H A D | regs-lcd.h | 27 #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ macro
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/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm/mach-pxa/include/mach/ |
H A D | regs-lcd.h | 27 #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ macro
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/dports/emulators/qemu42/qemu-4.2.1/hw/display/ |
H A D | pxa2xx_lcd.c | 101 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ macro 390 case FBR5: in pxa2xx_lcdc_read() 539 case FBR5: in pxa2xx_lcdc_write()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/display/ |
H A D | pxa2xx_lcd.c | 99 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ macro 388 case FBR5: in pxa2xx_lcdc_read() 537 case FBR5: in pxa2xx_lcdc_write()
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/dports/emulators/qemu5/qemu-5.2.0/hw/display/ |
H A D | pxa2xx_lcd.c | 101 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ macro 390 case FBR5: in pxa2xx_lcdc_read() 542 case FBR5: in pxa2xx_lcdc_write()
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/dports/emulators/qemu-utils/qemu-4.2.1/hw/display/ |
H A D | pxa2xx_lcd.c | 101 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ macro 390 case FBR5: in pxa2xx_lcdc_read() 539 case FBR5: in pxa2xx_lcdc_write()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/display/ |
H A D | pxa2xx_lcd.c | 101 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ 390 case FBR5: 539 case FBR5:
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/display/ |
H A D | pxa2xx_lcd.c | 101 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ macro 390 case FBR5: in pxa2xx_lcdc_read() 539 case FBR5: in pxa2xx_lcdc_write()
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/dports/emulators/qemu/qemu-6.2.0/hw/display/ |
H A D | pxa2xx_lcd.c | 101 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ macro 819 case FBR5: in pxa2xx_lcdc_read() 971 case FBR5: in pxa2xx_lcdc_write()
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/dports/emulators/qemu60/qemu-6.0.0/hw/display/ |
H A D | pxa2xx_lcd.c | 101 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ macro 819 case FBR5: in pxa2xx_lcdc_read() 971 case FBR5: in pxa2xx_lcdc_write()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/display/ |
H A D | pxa2xx_lcd.c | 101 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ macro 819 case FBR5: in pxa2xx_lcdc_read() 971 case FBR5: in pxa2xx_lcdc_write()
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ macro
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