FMT3I (reference) in projects: dports - OpenGrok search results

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Searched refs:FMT3I (Results 1 – 6 of 6) sorted by relevance

/dports/games/ioquake3-server/ioquake3-1.36/code/qcommon/
H A D	vm_sparc.c	93 #define TICC(COND) FMT3I(0,((COND<<6)\|0x3a)) 175 { "add", FMT3I(2, 0x00), ARG_RS1_SIMM13_RD, }, 177 { "and", FMT3I(2, 0x01), ARG_RS1_SIMM13_RD, }, 179 { "or", FMT3I(2, 0x02), ARG_RS1_SIMM13_RD, }, 222 { "ldx", FMT3I(3,0x0b), ARG_RS1_SIMM13_RD, }, 231 { "stx", FMT3I(3,0x0e), ARG_RS1_SIMM13_RD, }, 233 { "stw", FMT3I(3,0x04), ARG_RS1_SIMM13_RD, }, 235 { "sth", FMT3I(3,0x06), ARG_RS1_SIMM13_RD, }, 237 { "stb", FMT3I(3,0x05), ARG_RS1_SIMM13_RD, }, 240 { "ldf", FMT3I(3,0x20), ARG_RS1_SIMM13_RD, }, [all …]
/dports/games/ioquake3/ioquake3-1.36/code/qcommon/
H A D	vm_sparc.c	93 #define TICC(COND) FMT3I(0,((COND<<6)\|0x3a)) 175 { "add", FMT3I(2, 0x00), ARG_RS1_SIMM13_RD, }, 177 { "and", FMT3I(2, 0x01), ARG_RS1_SIMM13_RD, }, 179 { "or", FMT3I(2, 0x02), ARG_RS1_SIMM13_RD, }, 222 { "ldx", FMT3I(3,0x0b), ARG_RS1_SIMM13_RD, }, 231 { "stx", FMT3I(3,0x0e), ARG_RS1_SIMM13_RD, }, 233 { "stw", FMT3I(3,0x04), ARG_RS1_SIMM13_RD, }, 235 { "sth", FMT3I(3,0x06), ARG_RS1_SIMM13_RD, }, 237 { "stb", FMT3I(3,0x05), ARG_RS1_SIMM13_RD, }, 240 { "ldf", FMT3I(3,0x20), ARG_RS1_SIMM13_RD, }, [all …]
/dports/games/openarena/openarena-engine-source-0.8.8/code/qcommon/
H A D	vm_sparc.c	93 #define TICC(COND) FMT3I(0,((COND<<6)\|0x3a)) 175 { "add", FMT3I(2, 0x00), ARG_RS1_SIMM13_RD, }, 177 { "and", FMT3I(2, 0x01), ARG_RS1_SIMM13_RD, }, 179 { "or", FMT3I(2, 0x02), ARG_RS1_SIMM13_RD, }, 222 { "ldx", FMT3I(3,0x0b), ARG_RS1_SIMM13_RD, }, 231 { "stx", FMT3I(3,0x0e), ARG_RS1_SIMM13_RD, }, 233 { "stw", FMT3I(3,0x04), ARG_RS1_SIMM13_RD, }, 235 { "sth", FMT3I(3,0x06), ARG_RS1_SIMM13_RD, }, 237 { "stb", FMT3I(3,0x05), ARG_RS1_SIMM13_RD, }, 240 { "ldf", FMT3I(3,0x20), ARG_RS1_SIMM13_RD, }, [all …]
/dports/games/openarena-server/openarena-engine-source-0.8.8/code/qcommon/
H A D	vm_sparc.c	93 #define TICC(COND) FMT3I(0,((COND<<6)\|0x3a)) 175 { "add", FMT3I(2, 0x00), ARG_RS1_SIMM13_RD, }, 177 { "and", FMT3I(2, 0x01), ARG_RS1_SIMM13_RD, }, 179 { "or", FMT3I(2, 0x02), ARG_RS1_SIMM13_RD, }, 222 { "ldx", FMT3I(3,0x0b), ARG_RS1_SIMM13_RD, }, 231 { "stx", FMT3I(3,0x0e), ARG_RS1_SIMM13_RD, }, 233 { "stw", FMT3I(3,0x04), ARG_RS1_SIMM13_RD, }, 235 { "sth", FMT3I(3,0x06), ARG_RS1_SIMM13_RD, }, 237 { "stb", FMT3I(3,0x05), ARG_RS1_SIMM13_RD, }, 240 { "ldf", FMT3I(3,0x20), ARG_RS1_SIMM13_RD, }, [all …]
/dports/games/iortcw/iortcw-1.51c/MP/code/qcommon/
H A D	vm_sparc.c	93 #define TICC(COND) FMT3I(0,((COND<<6)\|0x3a)) 175 { "add", FMT3I(2, 0x00), ARG_RS1_SIMM13_RD, }, 177 { "and", FMT3I(2, 0x01), ARG_RS1_SIMM13_RD, }, 179 { "or", FMT3I(2, 0x02), ARG_RS1_SIMM13_RD, }, 222 { "ldx", FMT3I(3,0x0b), ARG_RS1_SIMM13_RD, }, 231 { "stx", FMT3I(3,0x0e), ARG_RS1_SIMM13_RD, }, 233 { "stw", FMT3I(3,0x04), ARG_RS1_SIMM13_RD, }, 235 { "sth", FMT3I(3,0x06), ARG_RS1_SIMM13_RD, }, 237 { "stb", FMT3I(3,0x05), ARG_RS1_SIMM13_RD, }, 240 { "ldf", FMT3I(3,0x20), ARG_RS1_SIMM13_RD, }, [all …]
/dports/games/iortcw/iortcw-1.51c/SP/code/qcommon/
H A D	vm_sparc.c	93 #define TICC(COND) FMT3I(0,((COND<<6)\|0x3a)) 175 { "add", FMT3I(2, 0x00), ARG_RS1_SIMM13_RD, }, 177 { "and", FMT3I(2, 0x01), ARG_RS1_SIMM13_RD, }, 179 { "or", FMT3I(2, 0x02), ARG_RS1_SIMM13_RD, }, 222 { "ldx", FMT3I(3,0x0b), ARG_RS1_SIMM13_RD, }, 231 { "stx", FMT3I(3,0x0e), ARG_RS1_SIMM13_RD, }, 233 { "stw", FMT3I(3,0x04), ARG_RS1_SIMM13_RD, }, 235 { "sth", FMT3I(3,0x06), ARG_RS1_SIMM13_RD, }, 237 { "stb", FMT3I(3,0x05), ARG_RS1_SIMM13_RD, }, 240 { "ldf", FMT3I(3,0x20), ARG_RS1_SIMM13_RD, }, [all …]