| /dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A64/translate/impl/ |
| H A D | floating_point_data_processing_two_register.cpp | 19 const IR::U32U64 result = ir.FPMul(operand1, operand2); in FMUL_float()
139 const IR::U32U64 result = ir.FPNeg(ir.FPMul(operand1, operand2)); in FNMUL_float()
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| H A D | simd_scalar_x_indexed_element.cpp | 42 return v.ir.FPMul(operand1, element); in MultiplyByElement()
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| /dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/A64/translate/impl/ |
| H A D | floating_point_data_processing_two_register.cpp | 19 const IR::U32U64 result = ir.FPMul(operand1, operand2, true); in FMUL_float()
139 const IR::U32U64 result = ir.FPNeg(ir.FPMul(operand1, operand2, true)); in FNMUL_float()
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| H A D | simd_scalar_x_indexed_element.cpp | 42 return v.ir.FPMul(operand1, element, true); in MultiplyByElement()
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| /dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/A64/translate/impl/ |
| H A D | floating_point_data_processing_two_register.cpp | 19 const IR::U32U64 result = ir.FPMul(operand1, operand2, true); in FMUL_float()
139 const IR::U32U64 result = ir.FPNeg(ir.FPMul(operand1, operand2, true)); in FNMUL_float()
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| H A D | simd_scalar_x_indexed_element.cpp | 42 return v.ir.FPMul(operand1, element, true); in MultiplyByElement()
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| /dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/A32/translate/impl/ |
| H A D | vfp.cpp | 136 const auto result = ir.FPMul(reg_n, reg_m, true); in vfp_VMUL()
156 const auto result = ir.FPAdd(reg_d, ir.FPMul(reg_n, reg_m, true), true); in vfp_VMLA()
176 const auto result = ir.FPAdd(reg_d, ir.FPNeg(ir.FPMul(reg_n, reg_m, true)), true); in vfp_VMLS()
195 const auto result = ir.FPNeg(ir.FPMul(reg_n, reg_m, true)); in vfp_VNMUL()
215 const auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPNeg(ir.FPMul(reg_n, reg_m, true)), true); in vfp_VNMLA()
235 const auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPMul(reg_n, reg_m, true), true); in vfp_VNMLS()
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| /dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/A32/translate/impl/ |
| H A D | vfp.cpp | 136 const auto result = ir.FPMul(reg_n, reg_m, true); in vfp_VMUL()
156 const auto result = ir.FPAdd(reg_d, ir.FPMul(reg_n, reg_m, true), true); in vfp_VMLA()
176 const auto result = ir.FPAdd(reg_d, ir.FPNeg(ir.FPMul(reg_n, reg_m, true)), true); in vfp_VMLS()
195 const auto result = ir.FPNeg(ir.FPMul(reg_n, reg_m, true)); in vfp_VNMUL()
215 const auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPNeg(ir.FPMul(reg_n, reg_m, true)), true); in vfp_VNMLA()
235 const auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPMul(reg_n, reg_m, true), true); in vfp_VNMLS()
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| /dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A32/translate/impl/ |
| H A D | vfp.cpp | 138 const auto result = ir.FPMul(reg_n, reg_m); in vfp_VMUL()
158 const auto result = ir.FPAdd(reg_d, ir.FPMul(reg_n, reg_m)); in vfp_VMLA()
178 const auto result = ir.FPAdd(reg_d, ir.FPNeg(ir.FPMul(reg_n, reg_m))); in vfp_VMLS()
197 const auto result = ir.FPNeg(ir.FPMul(reg_n, reg_m)); in vfp_VNMUL()
217 const auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPNeg(ir.FPMul(reg_n, reg_m))); in vfp_VNMLA()
237 const auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPMul(reg_n, reg_m)); in vfp_VNMLS()
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| /dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/ir/ |
| H A D | ir_emitter.h | 325 U32U64 FPMul(const U32U64& a, const U32U64& b);
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| /dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/ir/ |
| H A D | ir_emitter.h | 320 U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled);
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| /dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/ir/ |
| H A D | ir_emitter.h | 320 U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled);
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| /dports/www/firefox-esr/firefox-91.8.0/js/src/jit/arm64/vixl/ |
| H A D | Simulator-vixl.h | 2070 V(fmul, FPMul, true) \
2317 T FPMul(T op1, T op2);
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| /dports/www/firefox/firefox-99.0/js/src/jit/arm64/vixl/ |
| H A D | Simulator-vixl.h | 2070 V(fmul, FPMul, true) \
2317 T FPMul(T op1, T op2);
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| /dports/www/firefox-legacy/firefox-52.8.0esr/js/src/jit/arm64/vixl/ |
| H A D | Simulator-vixl.h | 2242 V(fmul, FPMul, true) \
2493 T FPMul(T op1, T op2);
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| /dports/mail/thunderbird/thunderbird-91.8.0/js/src/jit/arm64/vixl/ |
| H A D | Simulator-vixl.h | 2070 V(fmul, FPMul, true) \
2317 T FPMul(T op1, T op2);
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| /dports/lang/spidermonkey78/firefox-78.9.0/js/src/jit/arm64/vixl/ |
| H A D | Simulator-vixl.h | 2069 V(fmul, FPMul, true) \
2316 T FPMul(T op1, T op2);
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| /dports/lang/v8/v8-9.6.180.12/src/execution/arm64/ |
| H A D | simulator-arm64.h | 2042 V(fmul, FPMul, true) \
2222 T FPMul(T op1, T op2);
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| H A D | simulator-logic-arm64.cc | 2951 T Simulator::FPMul(T op1, T op2) { in FPMul() function in v8::internal::Simulator
2972 return FPMul(op1, op2); in FPMulx()
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| /dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 2023 V(fmul, FPMul, true) \
2202 T FPMul(T op1, T op2);
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| /dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 2023 V(fmul, FPMul, true) \
2203 T FPMul(T op1, T op2);
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| /dports/lang/spidermonkey60/firefox-60.9.0/js/src/jit/arm64/vixl/ |
| H A D | Simulator-vixl.h | 2241 V(fmul, FPMul, true) \
2492 T FPMul(T op1, T op2);
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| /dports/www/node10/node-v10.24.1/deps/v8/src/arm64/ |
| H A D | simulator-arm64.h | 1879 V(fmul, FPMul, true) \
2058 T FPMul(T op1, T op2);
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| /dports/databases/mongodb36/mongodb-src-r3.6.23/src/third_party/mozjs-45/extract/js/src/jit/arm64/vixl/ |
| H A D | Simulator-vixl.h | 2353 V(fmul, FPMul, true) \
2604 T FPMul(T op1, T op2);
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| /dports/devel/intel-graphics-compiler/intel-graphics-compiler-igc-1.0.9636/IGC/VectorCompiler/lib/GenXCodeGen/ |
| H A D | GenXPatternMatch.cpp | 2249 static FPMulLike FPMul; in get() local
2250 return FPMul; in get()
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