| /dports/devel/elfutils/elfutils-0.179/backends/ |
| H A D | s390_corenote.c | 66 #define FPR(at, n, dwreg) \ macro
71 FPR (1 + 0, 1, 16), /* f0 */
72 FPR (1 + 1, 1, 20), /* f1 */
73 FPR (1 + 2, 1, 17), /* f2 */
74 FPR (1 + 3, 1, 21), /* f3 */
75 FPR (1 + 4, 1, 18), /* f4 */
76 FPR (1 + 5, 1, 22), /* f5 */
77 FPR (1 + 6, 1, 19), /* f6 */
78 FPR (1 + 7, 1, 23), /* f7 */
79 FPR (1 + 8, 1, 24), /* f8 */
[all …]
|
| /dports/mail/py-alot/alot-0.9/tests/commands/ |
| H A D | utils_tests.py | 36 FPR = "F74091D4133F87D56B5D343C1974EC55FBC2D660" variable
81 ids = [FPR]
83 self.assertIn(FPR, actual)
94 self.assertIn(FPR, actual)
101 ids = [FPR]
118 ids = [FPR]
167 [crypto.get_key(FPR).fpr])
184 gpg_key = crypto.get_key(FPR)
189 self.assertIn(FPR, envelope.encrypt_keys)
198 gpg_key = crypto.get_key(FPR)
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
49 // 7: FPR 64-bit value.
53 // 10: FPR 128-bit value.
245 // => FPR 16 to FPR 32|64
246 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
49 // 7: FPR 64-bit value.
53 // 10: FPR 128-bit value.
245 // => FPR 16 to FPR 32|64
246 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
51 // 7: FPR 64-bit value.
55 // 10: FPR 128-bit value.
253 // => FPR 16 to FPR 32|64
254 // => FPR 32 to FPR 64
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
51 // 7: FPR 64-bit value.
55 // 10: FPR 128-bit value.
253 // => FPR 16 to FPR 32|64
254 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
49 // 7: FPR 64-bit value.
53 // 10: FPR 128-bit value.
245 // => FPR 16 to FPR 32|64
246 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
49 // 7: FPR 64-bit value.
53 // 10: FPR 128-bit value.
245 // => FPR 16 to FPR 32|64
246 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
49 // 7: FPR 64-bit value.
53 // 10: FPR 128-bit value.
245 // => FPR 16 to FPR 32|64
246 // => FPR 32 to FPR 64
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
49 // 7: FPR 64-bit value.
53 // 10: FPR 128-bit value.
245 // => FPR 16 to FPR 32|64
246 // => FPR 32 to FPR 64
[all …]
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
51 // 7: FPR 64-bit value.
55 // 10: FPR 128-bit value.
253 // => FPR 16 to FPR 32|64
254 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
51 // 7: FPR 64-bit value.
55 // 10: FPR 128-bit value.
253 // => FPR 16 to FPR 32|64
254 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
51 // 7: FPR 64-bit value.
55 // 10: FPR 128-bit value.
253 // => FPR 16 to FPR 32|64
254 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
49 // 7: FPR 64-bit value.
53 // 10: FPR 128-bit value.
245 // => FPR 16 to FPR 32|64
246 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
49 // 7: FPR 64-bit value.
53 // 10: FPR 128-bit value.
245 // => FPR 16 to FPR 32|64
246 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
49 // 7: FPR 64-bit value.
53 // 10: FPR 128-bit value.
245 // => FPR 16 to FPR 32|64
246 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 17 // 0: FPR 16-bit value.
19 // 1: FPR 32-bit value.
21 // 2: FPR 64-bit value.
23 // 3: FPR 128-bit value.
25 // 4: FPR 256-bit value.
27 // 5: FPR 512-bit value.
50 // 7: FPR 64-bit value.
54 // 10: FPR 128-bit value.
242 // => FPR 16 to FPR 32|64
243 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 17 // 0: FPR 16-bit value.
19 // 1: FPR 32-bit value.
21 // 2: FPR 64-bit value.
23 // 3: FPR 128-bit value.
25 // 4: FPR 256-bit value.
27 // 5: FPR 512-bit value.
50 // 7: FPR 64-bit value.
54 // 10: FPR 128-bit value.
242 // => FPR 16 to FPR 32|64
243 // => FPR 32 to FPR 64
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
51 // 7: FPR 64-bit value.
55 // 10: FPR 128-bit value.
253 // => FPR 16 to FPR 32|64
254 // => FPR 32 to FPR 64
[all …]
|
| /dports/sysutils/vector/lucet-d4fc14a03bdb99ac83173d27fddf1aca48412a86/wasmtime/cranelift/codegen/src/isa/riscv/ |
| H A D | registers.rs | 9 use super::{FPR, GPR, INFO};
43 assert!(!FPR.contains(GPR.unit(0))); in classes()
44 assert!(!FPR.contains(GPR.unit(31))); in classes()
45 assert!(!GPR.contains(FPR.unit(0))); in classes()
46 assert!(!GPR.contains(FPR.unit(31))); in classes()
47 assert!(FPR.contains(FPR.unit(0))); in classes()
48 assert!(FPR.contains(FPR.unit(31))); in classes()
|
| /dports/www/geckodriver/mozilla-central-e9783a644016aa9b317887076618425586730d73/testing/geckodriver/cargo-crates/cranelift-codegen-0.44.0/src/isa/riscv/ |
| H A D | registers.rs | 9 use super::{FPR, GPR, INFO};
43 assert!(!FPR.contains(GPR.unit(0))); in classes()
44 assert!(!FPR.contains(GPR.unit(31))); in classes()
45 assert!(!GPR.contains(FPR.unit(0))); in classes()
46 assert!(!GPR.contains(FPR.unit(31))); in classes()
47 assert!(FPR.contains(FPR.unit(0))); in classes()
48 assert!(FPR.contains(FPR.unit(31))); in classes()
|
| /dports/www/firefox/firefox-99.0/third_party/rust/cranelift-codegen/src/isa/riscv/ |
| H A D | registers.rs | 9 use super::{FPR, GPR, INFO};
43 assert!(!FPR.contains(GPR.unit(0))); in classes()
44 assert!(!FPR.contains(GPR.unit(31))); in classes()
45 assert!(!GPR.contains(FPR.unit(0))); in classes()
46 assert!(!GPR.contains(FPR.unit(31))); in classes()
47 assert!(FPR.contains(FPR.unit(0))); in classes()
48 assert!(FPR.contains(FPR.unit(31))); in classes()
|
| /dports/mail/thunderbird/thunderbird-91.8.0/third_party/rust/cranelift-codegen/src/isa/riscv/ |
| H A D | registers.rs | 9 use super::{FPR, GPR, INFO};
43 assert!(!FPR.contains(GPR.unit(0))); in classes()
44 assert!(!FPR.contains(GPR.unit(31))); in classes()
45 assert!(!GPR.contains(FPR.unit(0))); in classes()
46 assert!(!GPR.contains(FPR.unit(31))); in classes()
47 assert!(FPR.contains(FPR.unit(0))); in classes()
48 assert!(FPR.contains(FPR.unit(31))); in classes()
|
| /dports/lang/rust/rustc-1.58.1-src/vendor/cranelift-codegen/src/isa/legacy/riscv/ |
| H A D | registers.rs | 9 use super::{FPR, GPR, INFO};
43 assert!(!FPR.contains(GPR.unit(0))); in classes()
44 assert!(!FPR.contains(GPR.unit(31))); in classes()
45 assert!(!GPR.contains(FPR.unit(0))); in classes()
46 assert!(!GPR.contains(FPR.unit(31))); in classes()
47 assert!(FPR.contains(FPR.unit(0))); in classes()
48 assert!(FPR.contains(FPR.unit(31))); in classes()
|
| /dports/www/firefox-esr/firefox-91.8.0/third_party/rust/cranelift-codegen/src/isa/riscv/ |
| H A D | registers.rs | 9 use super::{FPR, GPR, INFO};
43 assert!(!FPR.contains(GPR.unit(0))); in classes()
44 assert!(!FPR.contains(GPR.unit(31))); in classes()
45 assert!(!GPR.contains(FPR.unit(0))); in classes()
46 assert!(!GPR.contains(FPR.unit(31))); in classes()
47 assert!(FPR.contains(FPR.unit(0))); in classes()
48 assert!(FPR.contains(FPR.unit(31))); in classes()
|