/dports/www/firefox-esr/firefox-91.8.0/js/src/jit/arm64/vixl/ |
H A D | Simulator-vixl.cpp | 1900 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1902 case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1917 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1923 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1941 set_wreg(dst, FPToUInt32(sreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1947 set_wreg(dst, FPToUInt32(dreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1956 case FCVTNU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1958 case FCVTNU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1964 case FCVTZU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPZero)); break; in VisitFPIntegerConvert() 1966 case FCVTZU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPZero)); break; in VisitFPIntegerConvert() [all …]
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H A D | Simulator-vixl.h | 2294 uint32_t FPToUInt32(double value, FPRounding rmode);
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H A D | Logic-vixl.cpp | 3681 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) { in FPToUInt32() function in vixl::Simulator 4259 dst.SetUint(vform, i, FPToUInt32(op, rounding_mode)); in fcvtu()
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/dports/www/firefox/firefox-99.0/js/src/jit/arm64/vixl/ |
H A D | Simulator-vixl.cpp | 1900 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1902 case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1917 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1923 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1941 set_wreg(dst, FPToUInt32(sreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1947 set_wreg(dst, FPToUInt32(dreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1956 case FCVTNU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1958 case FCVTNU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1964 case FCVTZU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPZero)); break; in VisitFPIntegerConvert() 1966 case FCVTZU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPZero)); break; in VisitFPIntegerConvert() [all …]
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H A D | Simulator-vixl.h | 2294 uint32_t FPToUInt32(double value, FPRounding rmode);
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H A D | Logic-vixl.cpp | 3681 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) { in FPToUInt32() function in vixl::Simulator 4259 dst.SetUint(vform, i, FPToUInt32(op, rounding_mode)); in fcvtu()
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/dports/mail/thunderbird/thunderbird-91.8.0/js/src/jit/arm64/vixl/ |
H A D | Simulator-vixl.cpp | 1900 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1902 case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1917 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1923 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1941 set_wreg(dst, FPToUInt32(sreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1947 set_wreg(dst, FPToUInt32(dreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1956 case FCVTNU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1958 case FCVTNU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1964 case FCVTZU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPZero)); break; in VisitFPIntegerConvert() 1966 case FCVTZU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPZero)); break; in VisitFPIntegerConvert() [all …]
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H A D | Simulator-vixl.h | 2294 uint32_t FPToUInt32(double value, FPRounding rmode);
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H A D | Logic-vixl.cpp | 3681 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) { in FPToUInt32() function in vixl::Simulator 4259 dst.SetUint(vform, i, FPToUInt32(op, rounding_mode)); in fcvtu()
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/dports/www/firefox-legacy/firefox-52.8.0esr/js/src/jit/arm64/vixl/ |
H A D | Simulator-vixl.cpp | 1863 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break; 1865 case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break; 1880 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); 1886 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); 1904 set_wreg(dst, FPToUInt32(sreg(src), FPPositiveInfinity)); 1910 set_wreg(dst, FPToUInt32(dreg(src), FPPositiveInfinity)); 1919 case FCVTNU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); break; 1921 case FCVTNU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); break; 1927 case FCVTZU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPZero)); break; 1929 case FCVTZU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPZero)); break; [all …]
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H A D | Simulator-vixl.h | 2471 uint32_t FPToUInt32(double value, FPRounding rmode);
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H A D | Logic-vixl.cpp | 3842 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) { in FPToUInt32() function in vixl::Simulator 4418 dst.SetUint(vform, i, FPToUInt32(op, rounding_mode)); in fcvtu()
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/dports/lang/spidermonkey60/firefox-60.9.0/js/src/jit/arm64/vixl/ |
H A D | Simulator-vixl.cpp | 1894 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1896 case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1911 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1917 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1935 set_wreg(dst, FPToUInt32(sreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1941 set_wreg(dst, FPToUInt32(dreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1950 case FCVTNU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1952 case FCVTNU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1958 case FCVTZU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPZero)); break; in VisitFPIntegerConvert() 1960 case FCVTZU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPZero)); break; in VisitFPIntegerConvert() [all …]
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H A D | Logic-vixl.cpp | 3842 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) { in FPToUInt32() function in vixl::Simulator 4418 dst.SetUint(vform, i, FPToUInt32(op, rounding_mode)); in fcvtu()
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/dports/lang/spidermonkey78/firefox-78.9.0/js/src/jit/arm64/vixl/ |
H A D | Simulator-vixl.cpp | 1900 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1902 case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1917 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1923 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1941 set_wreg(dst, FPToUInt32(sreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1947 set_wreg(dst, FPToUInt32(dreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1956 case FCVTNU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1958 case FCVTNU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1964 case FCVTZU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPZero)); break; in VisitFPIntegerConvert() 1966 case FCVTZU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPZero)); break; in VisitFPIntegerConvert() [all …]
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H A D | Simulator-vixl.h | 2293 uint32_t FPToUInt32(double value, FPRounding rmode);
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/dports/databases/mongodb36/mongodb-src-r3.6.23/src/third_party/mozjs-45/extract/js/src/jit/arm64/vixl/ |
H A D | Simulator-vixl.cpp | 1880 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1882 case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 1897 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1903 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 1921 set_wreg(dst, FPToUInt32(sreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1927 set_wreg(dst, FPToUInt32(dreg(src), FPPositiveInfinity)); in VisitFPIntegerConvert() 1936 case FCVTNU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1938 case FCVTNU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 1944 case FCVTZU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPZero)); break; in VisitFPIntegerConvert() 1946 case FCVTZU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPZero)); break; in VisitFPIntegerConvert() [all …]
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/dports/lang/v8/v8-9.6.180.12/src/execution/arm64/ |
H A D | simulator-arm64.cc | 2714 set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); in VisitFPIntegerConvert() 2720 set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); in VisitFPIntegerConvert() 2738 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 2744 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 2762 set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); in VisitFPIntegerConvert() 2768 set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); in VisitFPIntegerConvert() 2786 set_wreg(dst, FPToUInt32(sreg(src), FPZero)); in VisitFPIntegerConvert() 2792 set_wreg(dst, FPToUInt32(dreg(src), FPZero)); in VisitFPIntegerConvert()
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H A D | simulator-logic-arm64.cc | 3230 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) { in FPToUInt32() function in v8::internal::Simulator 3784 dst.SetUint(vform, i, FPToUInt32(op, rounding_mode)); in fcvtu()
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/dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/execution/arm64/ |
H A D | simulator-arm64.cc | 2676 set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); in VisitFPIntegerConvert() 2682 set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); in VisitFPIntegerConvert() 2700 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 2706 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 2724 set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); in VisitFPIntegerConvert() 2730 set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); in VisitFPIntegerConvert() 2748 set_wreg(dst, FPToUInt32(sreg(src), FPZero)); in VisitFPIntegerConvert() 2754 set_wreg(dst, FPToUInt32(dreg(src), FPZero)); in VisitFPIntegerConvert()
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H A D | simulator-logic-arm64.cc | 3240 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) { in FPToUInt32() function in v8::internal::Simulator 3745 dst.SetUint(vform, i, FPToUInt32(op, rounding_mode)); in fcvtu()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/execution/arm64/ |
H A D | simulator-arm64.cc | 2676 set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); in VisitFPIntegerConvert() 2682 set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); in VisitFPIntegerConvert() 2700 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 2706 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 2724 set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); in VisitFPIntegerConvert() 2730 set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); in VisitFPIntegerConvert() 2748 set_wreg(dst, FPToUInt32(sreg(src), FPZero)); in VisitFPIntegerConvert() 2754 set_wreg(dst, FPToUInt32(dreg(src), FPZero)); in VisitFPIntegerConvert()
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H A D | simulator-logic-arm64.cc | 3240 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) { in FPToUInt32() function in v8::internal::Simulator 3804 dst.SetUint(vform, i, FPToUInt32(op, rounding_mode)); in fcvtu()
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/dports/www/node10/node-v10.24.1/deps/v8/src/arm64/ |
H A D | simulator-arm64.cc | 2548 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 2550 case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break; in VisitFPIntegerConvert() 2565 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 2571 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert() 2580 case FCVTNU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 2582 case FCVTNU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); break; in VisitFPIntegerConvert() 2588 case FCVTZU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPZero)); break; in VisitFPIntegerConvert() 2590 case FCVTZU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPZero)); break; in VisitFPIntegerConvert()
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H A D | simulator-logic-arm64.cc | 3239 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) { in FPToUInt32() function in v8::internal::Simulator 3744 dst.SetUint(vform, i, FPToUInt32(op, rounding_mode)); in fcvtu()
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