Home
last modified time | relevance | path

Searched refs:FP_ENDIAN_IDX (Results 1 – 25 of 48) sorted by relevance

12

/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/
H A Dcpu.c49 fpr->w[FP_ENDIAN_IDX], fpr->d,
51 (double)fpr->fs[FP_ENDIAN_IDX],
52 (double)fpr->fs[!FP_ENDIAN_IDX]);
56 tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX];
57 tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX];
59 tmp.w[FP_ENDIAN_IDX], tmp.d,
61 (double)tmp.fs[FP_ENDIAN_IDX],
62 (double)tmp.fs[!FP_ENDIAN_IDX]);
H A Dgdbstub.c46 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
105 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
H A Dcpu.h39 # define FP_ENDIAN_IDX 1
41 # define FP_ENDIAN_IDX 0
/dports/emulators/qemu/qemu-6.2.0/target/mips/
H A Dcpu.c49 fpr->w[FP_ENDIAN_IDX], fpr->d, in fpu_dump_fpr()
51 (double)fpr->fs[FP_ENDIAN_IDX], in fpu_dump_fpr()
52 (double)fpr->fs[!FP_ENDIAN_IDX]); in fpu_dump_fpr()
56 tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX]; in fpu_dump_fpr()
57 tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX]; in fpu_dump_fpr()
59 tmp.w[FP_ENDIAN_IDX], tmp.d, in fpu_dump_fpr()
61 (double)tmp.fs[FP_ENDIAN_IDX], in fpu_dump_fpr()
62 (double)tmp.fs[!FP_ENDIAN_IDX]); in fpu_dump_fpr()
H A Dgdbstub.c46 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); in mips_cpu_gdb_read_register()
105 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; in mips_cpu_gdb_write_register()
H A Dcpu.h39 # define FP_ENDIAN_IDX 1 macro
41 # define FP_ENDIAN_IDX 0 macro
/dports/emulators/qemu-utils/qemu-4.2.1/target/mips/
H A Dgdbstub.c45 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); in mips_cpu_gdb_read_register()
104 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; in mips_cpu_gdb_write_register()
H A Dcpu.h38 # define FP_ENDIAN_IDX 1 macro
40 # define FP_ENDIAN_IDX 0 macro
H A Dkvm.c595 &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); in kvm_mips_put_fpu_registers()
675 &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); in kvm_mips_get_fpu_registers()
/dports/emulators/qemu5/qemu-5.2.0/target/mips/
H A Dgdbstub.c45 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); in mips_cpu_gdb_read_register()
104 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; in mips_cpu_gdb_write_register()
H A Dcpu.h39 # define FP_ENDIAN_IDX 1 macro
41 # define FP_ENDIAN_IDX 0 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/
H A Dgdbstub.c45 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); in mips_cpu_gdb_read_register()
104 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; in mips_cpu_gdb_write_register()
H A Dcpu.h38 # define FP_ENDIAN_IDX 1 macro
40 # define FP_ENDIAN_IDX 0 macro
H A Dkvm.c595 &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); in kvm_mips_put_fpu_registers()
675 &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); in kvm_mips_get_fpu_registers()
/dports/emulators/qemu42/qemu-4.2.1/target/mips/
H A Dgdbstub.c45 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); in mips_cpu_gdb_read_register()
104 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; in mips_cpu_gdb_write_register()
H A Dcpu.h38 # define FP_ENDIAN_IDX 1 macro
40 # define FP_ENDIAN_IDX 0 macro
H A Dkvm.c595 &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); in kvm_mips_put_fpu_registers()
675 &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); in kvm_mips_get_fpu_registers()
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dgdbstub.c46 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); in mips_cpu_gdb_read_register()
105 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; in mips_cpu_gdb_write_register()
H A Dcpu.h39 # define FP_ENDIAN_IDX 1 macro
41 # define FP_ENDIAN_IDX 0 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/
H A Dgdbstub.c46 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); in mips_cpu_gdb_read_register()
106 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; in mips_cpu_gdb_write_register()
H A Dcpu.h42 # define FP_ENDIAN_IDX 1 macro
44 # define FP_ENDIAN_IDX 0 macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/
H A Dgdbstub.c48 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); in mips_cpu_gdb_read_register()
98 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; in mips_cpu_gdb_write_register()
H A Dcpu.h43 # define FP_ENDIAN_IDX 1 macro
45 # define FP_ENDIAN_IDX 0 macro
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dcpu.h92 # define FP_ENDIAN_IDX 1 macro
94 # define FP_ENDIAN_IDX 0 macro
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dcpu.h92 # define FP_ENDIAN_IDX 1
94 # define FP_ENDIAN_IDX 0

12