/dports/devel/plan9port/plan9port-1f098efb7370a0b28306d10681e21883fb1c1507/src/libmach/ |
H A D | machamd64.c | 50 #define FP_REG(x) (FP_CTL(8)+16*(x)) macro 93 {"M0", FP_REG(0), RFLT, 'F'}, /* assumes double */ 94 {"M1", FP_REG(1), RFLT, 'F'}, 95 {"M2", FP_REG(2), RFLT, 'F'}, 96 {"M3", FP_REG(3), RFLT, 'F'}, 97 {"M4", FP_REG(4), RFLT, 'F'}, 98 {"M5", FP_REG(5), RFLT, 'F'}, 99 {"M6", FP_REG(6), RFLT, 'F'}, 100 {"M7", FP_REG(7), RFLT, 'F'},
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H A D | machpower.c | 1246 #define FP_REG(x) (R31+4+8*(x)) macro 1295 {"F0", FP_REG(0), RFLT, 'F'}, 1296 {"F1", FP_REG(1), RFLT, 'F'}, 1297 {"F2", FP_REG(2), RFLT, 'F'}, 1298 {"F3", FP_REG(3), RFLT, 'F'}, 1299 {"F4", FP_REG(4), RFLT, 'F'}, 1300 {"F5", FP_REG(5), RFLT, 'F'}, 1301 {"F6", FP_REG(6), RFLT, 'F'}, 1302 {"F7", FP_REG(7), RFLT, 'F'}, 1303 {"F8", FP_REG(8), RFLT, 'F'}, [all …]
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H A D | mach386.c | 14 #define FP_REG(x) (FP_CTL(7)+10*(x)) macro 73 {"F0", FP_REG(7), RFLT, '3'}, 74 {"F1", FP_REG(6), RFLT, '3'}, 75 {"F2", FP_REG(5), RFLT, '3'}, 76 {"F3", FP_REG(4), RFLT, '3'}, 77 {"F4", FP_REG(3), RFLT, '3'}, 78 {"F5", FP_REG(2), RFLT, '3'}, 79 {"F6", FP_REG(1), RFLT, '3'}, 80 {"F7", FP_REG(0), RFLT, '3'},
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/dports/devel/elfutils/elfutils-0.179/backends/ |
H A D | aarch64_unwind.c | 34 #define FP_REG 29 macro 59 if (!getfunc(FP_REG, 1, &fp, arg)) in EBLHOOK() 77 setfunc(FP_REG, 1, &newFp, arg); in EBLHOOK()
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/dports/devel/libunwind/libunwind-1.5.0/src/mips/ |
H A D | Gstep.c | 123 #define FP_REG UNW_MIPS_R30 in _step_n64() macro 139 DWARF_GET_LOC (c->dwarf.loc[FP_REG])); in _step_n64() 142 ret = dwarf_get (&c->dwarf, c->dwarf.loc[FP_REG], ¤t_fp_val); in _step_n64() 146 DWARF_GET_LOC (c->dwarf.loc[FP_REG])); in _step_n64() 164 up_fp_loc = c->dwarf.loc[FP_REG]; in _step_n64() 177 c->dwarf.loc[FP_REG] = up_fp_loc; in _step_n64() 191 c->dwarf.loc[FP_REG] = up_fp_loc; in _step_n64()
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/dports/java/openjdk16/jdk16u-jdk-16.0.2-7-1/src/jdk.incubator.foreign/share/classes/jdk/internal/foreign/abi/x64/sysv/ |
H A D | SysVVaList.java | 71 … private static final MemoryLayout FP_REG = MemoryLayout.ofValueBits(128, ByteOrder.nativeOrder()); field in SysVVaList 80 FP_REG.withName("%xmm0"), 81 FP_REG.withName("%xmm1"), 82 FP_REG.withName("%xmm2"), 83 FP_REG.withName("%xmm3"), 84 FP_REG.withName("%xmm4"), 85 FP_REG.withName("%xmm5"), 86 FP_REG.withName("%xmm6"), 87 FP_REG.withName("%xmm7") 103 private static final int FP_SLOT_SIZE = (int) FP_REG.byteSize();
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/dports/java/openjdk17/jdk17u-jdk-17.0.1-12-1/src/jdk.incubator.foreign/share/classes/jdk/internal/foreign/abi/x64/sysv/ |
H A D | SysVVaList.java | 71 … private static final MemoryLayout FP_REG = MemoryLayout.valueLayout(128, ByteOrder.nativeOrder()); field in SysVVaList 80 FP_REG.withName("%xmm0"), 81 FP_REG.withName("%xmm1"), 82 FP_REG.withName("%xmm2"), 83 FP_REG.withName("%xmm3"), 84 FP_REG.withName("%xmm4"), 85 FP_REG.withName("%xmm5"), 86 FP_REG.withName("%xmm6"), 87 FP_REG.withName("%xmm7") 103 private static final int FP_SLOT_SIZE = (int) FP_REG.byteSize();
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/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/VEX/useful/ |
H A D | x87_to_vex_and_back.c | 41 #define FP_REG(ii) (10*(7-(ii))) macro 65 convert_f80le_to_f64le( &x87->reg[FP_REG(r)], (UChar*)&vexRegs[r] ); in x87_to_vex() 101 convert_f64le_to_f80le( (UChar*)&vexRegs[r], &x87->reg[FP_REG(r)] ); in vex_to_x87() 105 convert_f64le_to_f80le( (UChar*)&vexRegs[r], &x87->reg[FP_REG(r)] ); in vex_to_x87() 232 for (k = 0, j = FP_REG(i)+9; k < 10; k++,j--) in printFpuState()
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H A D | show_fp_state.c | 33 #define FP_REG(ii) (10*(7-(ii))) macro 101 for (k = 0, j = FP_REG(i)+9; k < 10; k++,j--) in printFpuState()
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/dports/devel/valgrind/valgrind-dragonfly-dragonfly/VEX/useful/ |
H A D | x87_to_vex_and_back.c | 41 #define FP_REG(ii) (10*(7-(ii))) macro 65 convert_f80le_to_f64le( &x87->reg[FP_REG(r)], (UChar*)&vexRegs[r] ); in x87_to_vex() 101 convert_f64le_to_f80le( (UChar*)&vexRegs[r], &x87->reg[FP_REG(r)] ); in vex_to_x87() 105 convert_f64le_to_f80le( (UChar*)&vexRegs[r], &x87->reg[FP_REG(r)] ); in vex_to_x87() 232 for (k = 0, j = FP_REG(i)+9; k < 10; k++,j--) in printFpuState()
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H A D | show_fp_state.c | 33 #define FP_REG(ii) (10*(7-(ii))) macro 101 for (k = 0, j = FP_REG(i)+9; k < 10; k++,j--) in printFpuState()
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/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/coregrind/m_debuginfo/ |
H A D | readdwarf.c | 1692 # define FP_REG 5 macro 1696 # define FP_REG 6 macro 1700 # define FP_REG 1 macro 1704 # define FP_REG 1 macro 1708 # define FP_REG 12 macro 1712 # define FP_REG 29 macro 1716 # define FP_REG 5 macro 1720 # define FP_REG 6 macro 1728 # define FP_REG 30 macro 1732 # define FP_REG 30 macro [all …]
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/dports/devel/valgrind/valgrind-dragonfly-dragonfly/coregrind/m_debuginfo/ |
H A D | readdwarf.c | 1692 # define FP_REG 5 macro 1696 # define FP_REG 6 macro 1700 # define FP_REG 1 macro 1704 # define FP_REG 1 macro 1708 # define FP_REG 12 macro 1712 # define FP_REG 29 macro 1716 # define FP_REG 5 macro 1720 # define FP_REG 6 macro 1728 # define FP_REG 30 macro 1732 # define FP_REG 30 macro [all …]
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/dports/security/py-pyvex/pyvex-9.0.5405/vex/priv/ |
H A D | guest_generic_x87.h | 95 #define FP_REG(ii) (10*(7-(ii))) macro
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/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/VEX/priv/ |
H A D | guest_generic_x87.h | 95 #define FP_REG(ii) (10*(7-(ii))) macro
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/dports/devel/valgrind/valgrind-dragonfly-dragonfly/VEX/priv/ |
H A D | guest_generic_x87.h | 95 #define FP_REG(ii) (10*(7-(ii))) macro
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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/ |
H A D | call-argument-types.ll | 660 ; MESA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x800{{$}} 661 ; HSA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x800{{$}} 665 ; GCN-DAG: buffer_store_byte [[VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:8 666 ; GCN-DAG: buffer_store_dword [[VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:12 668 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offse… 669 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offse… 675 ; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] off… 676 ; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] off…
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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/ |
H A D | call-argument-types.ll | 673 ; MESA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x800{{$}} 674 ; HSA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x800{{$}} 678 ; GCN-DAG: buffer_store_byte [[VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:8 679 ; GCN-DAG: buffer_store_dword [[VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:12 681 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offse… 682 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offse… 688 ; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] off… 689 ; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] off…
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/dports/java/openjdk17/jdk17u-jdk-17.0.1-12-1/src/jdk.incubator.foreign/share/classes/jdk/internal/foreign/abi/aarch64/linux/ |
H A D | LinuxAArch64VaList.java | 80 private static final MemoryLayout FP_REG field in LinuxAArch64VaList 86 = MemoryLayout.sequenceLayout(MAX_REGISTER_ARGUMENTS, FP_REG); 89 private static final int FP_SLOT_SIZE = (int) FP_REG.byteSize();
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/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/ft32/ |
H A D | ft32.md | 29 (FP_REG 0) 911 ;; (reg:SI FP_REG)) 922 [(set (reg:SI FP_REG) 923 (mem:SI (reg:SI FP_REG))) 925 (plus:SI (reg:SI FP_REG)
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/dports/lang/gcc9/gcc-9.4.0/gcc/config/ft32/ |
H A D | ft32.md | 29 (FP_REG 0) 911 ;; (reg:SI FP_REG)) 922 [(set (reg:SI FP_REG) 923 (mem:SI (reg:SI FP_REG))) 925 (plus:SI (reg:SI FP_REG)
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/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/ft32/ |
H A D | ft32.md | 29 (FP_REG 0) 911 ;; (reg:SI FP_REG)) 922 [(set (reg:SI FP_REG) 923 (mem:SI (reg:SI FP_REG))) 925 (plus:SI (reg:SI FP_REG)
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/dports/lang/gnat_util/gcc-6-20180516/gcc/config/ft32/ |
H A D | ft32.md | 29 (FP_REG 0) 907 ;; (reg:SI FP_REG)) 918 [(set (reg:SI FP_REG) 919 (mem:SI (reg:SI FP_REG))) 921 (plus:SI (reg:SI FP_REG)
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/dports/devel/avr-gcc/gcc-10.2.0/gcc/config/ft32/ |
H A D | ft32.md | 29 (FP_REG 0) 911 ;; (reg:SI FP_REG)) 922 [(set (reg:SI FP_REG) 923 (mem:SI (reg:SI FP_REG))) 925 (plus:SI (reg:SI FP_REG)
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/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/ft32/ |
H A D | ft32.md | 29 (FP_REG 0) 911 ;; (reg:SI FP_REG)) 922 [(set (reg:SI FP_REG) 923 (mem:SI (reg:SI FP_REG))) 925 (plus:SI (reg:SI FP_REG)
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