Home
last modified time | relevance | path

Searched refs:FP_REG_RTX_P (Results 1 – 25 of 125) sorted by relevance

12345

/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/riscv/
H A Driscv.h281 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
H A Driscv.c1723 gcc_assert (!FP_REG_RTX_P (op)); in riscv_subword()
1739 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) in riscv_split_64bit_move_p()
1740 || (FP_REG_RTX_P (dest) && MEM_P (src)) in riscv_split_64bit_move_p()
1741 || (FP_REG_RTX_P (src) && MEM_P (dest)) in riscv_split_64bit_move_p()
1742 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) in riscv_split_64bit_move_p()
/dports/lang/gcc9/gcc-9.4.0/gcc/config/riscv/
H A Driscv.h287 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/riscv/
H A Driscv.h281 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
H A Driscv.c1720 gcc_assert (!FP_REG_RTX_P (op)); in riscv_subword()
1736 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) in riscv_split_64bit_move_p()
1737 || (FP_REG_RTX_P (dest) && MEM_P (src)) in riscv_split_64bit_move_p()
1738 || (FP_REG_RTX_P (src) && MEM_P (dest)) in riscv_split_64bit_move_p()
1739 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) in riscv_split_64bit_move_p()
/dports/devel/avr-gcc/gcc-10.2.0/gcc/config/riscv/
H A Driscv.h303 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
H A Driscv.c1863 gcc_assert (!FP_REG_RTX_P (op)); in riscv_subword()
1879 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) in riscv_split_64bit_move_p()
1880 || (FP_REG_RTX_P (dest) && MEM_P (src)) in riscv_split_64bit_move_p()
1881 || (FP_REG_RTX_P (src) && MEM_P (dest)) in riscv_split_64bit_move_p()
1882 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) in riscv_split_64bit_move_p()
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/riscv/
H A Driscv.h281 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
H A Driscv.c1723 gcc_assert (!FP_REG_RTX_P (op)); in riscv_subword()
1739 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) in riscv_split_64bit_move_p()
1740 || (FP_REG_RTX_P (dest) && MEM_P (src)) in riscv_split_64bit_move_p()
1741 || (FP_REG_RTX_P (src) && MEM_P (dest)) in riscv_split_64bit_move_p()
1742 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) in riscv_split_64bit_move_p()
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/riscv/
H A Driscv.h303 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
H A Driscv.c1863 gcc_assert (!FP_REG_RTX_P (op)); in riscv_subword()
1879 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) in riscv_split_64bit_move_p()
1880 || (FP_REG_RTX_P (dest) && MEM_P (src)) in riscv_split_64bit_move_p()
1881 || (FP_REG_RTX_P (src) && MEM_P (dest)) in riscv_split_64bit_move_p()
1882 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) in riscv_split_64bit_move_p()
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/riscv/
H A Driscv.h281 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
H A Driscv.c1723 gcc_assert (!FP_REG_RTX_P (op)); in riscv_subword()
1739 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) in riscv_split_64bit_move_p()
1740 || (FP_REG_RTX_P (dest) && MEM_P (src)) in riscv_split_64bit_move_p()
1741 || (FP_REG_RTX_P (src) && MEM_P (dest)) in riscv_split_64bit_move_p()
1742 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) in riscv_split_64bit_move_p()
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/riscv/
H A Driscv.h281 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
H A Driscv.c1723 gcc_assert (!FP_REG_RTX_P (op)); in riscv_subword()
1739 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) in riscv_split_64bit_move_p()
1740 || (FP_REG_RTX_P (dest) && MEM_P (src)) in riscv_split_64bit_move_p()
1741 || (FP_REG_RTX_P (src) && MEM_P (dest)) in riscv_split_64bit_move_p()
1742 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) in riscv_split_64bit_move_p()
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/riscv/
H A Driscv.h287 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
H A Driscv.c1806 gcc_assert (!FP_REG_RTX_P (op)); in riscv_subword()
1822 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) in riscv_split_64bit_move_p()
1823 || (FP_REG_RTX_P (dest) && MEM_P (src)) in riscv_split_64bit_move_p()
1824 || (FP_REG_RTX_P (src) && MEM_P (dest)) in riscv_split_64bit_move_p()
1825 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) in riscv_split_64bit_move_p()
/dports/lang/gcc10/gcc-10.3.0/gcc/config/riscv/
H A Driscv.h303 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/riscv/
H A Driscv.h287 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
/dports/lang/gcc8/gcc-8.5.0/gcc/config/riscv/
H A Driscv.h281 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
H A Driscv.c1723 gcc_assert (!FP_REG_RTX_P (op)); in riscv_subword()
1739 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) in riscv_split_64bit_move_p()
1740 || (FP_REG_RTX_P (dest) && MEM_P (src)) in riscv_split_64bit_move_p()
1741 || (FP_REG_RTX_P (src) && MEM_P (dest)) in riscv_split_64bit_move_p()
1742 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) in riscv_split_64bit_move_p()
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/riscv/
H A Driscv.h353 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/riscv/
H A Driscv.h348 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/riscv/
H A Driscv.h348 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro
/dports/lang/gcc11/gcc-11.2.0/gcc/config/riscv/
H A Driscv.h348 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) macro

12345