/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | m10300-opc.c | 382 #define FSN2 (FSN1+1) macro 386 #define FSN3 (FSN2+1) 1128 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1134 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1140 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1146 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1152 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1153 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1154 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1155 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | m10300-opc.c | 384 #define FSN2 (FSN1+1) macro 388 #define FSN3 (FSN2+1) 1130 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1136 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1142 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1148 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1154 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1155 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1156 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1157 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | m10300-opc.c | 384 #define FSN2 (FSN1+1) macro 388 #define FSN3 (FSN2+1) 1130 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1136 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1142 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1148 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1154 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1155 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1156 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1157 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | m10300-opc.c | 381 #define FSN2 (FSN1+1) macro 385 #define FSN3 (FSN2+1) 1127 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1133 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1139 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1145 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1151 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1152 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1153 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1154 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | m10300-opc.c | 384 #define FSN2 (FSN1+1) macro 388 #define FSN3 (FSN2+1) 1130 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1136 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1142 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1148 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1154 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1155 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1156 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1157 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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/dports/devel/avr-gdb/gdb-7.3.1/opcodes/ |
H A D | m10300-opc.c | 385 #define FSN2 (FSN1+1) macro 389 #define FSN3 (FSN2+1) 1131 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1137 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1143 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1149 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1155 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1156 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1157 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1158 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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/dports/devel/gdb761/gdb-7.6.1/opcodes/ |
H A D | m10300-opc.c | 385 #define FSN2 (FSN1+1) macro 389 #define FSN3 (FSN2+1) 1131 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1137 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1143 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1149 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1155 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1156 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1157 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1158 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | m10300-opc.c | 384 #define FSN2 (FSN1+1) macro 388 #define FSN3 (FSN2+1) 1130 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1136 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1142 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1148 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1154 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1155 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1156 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1157 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | m10300-opc.c | 384 #define FSN2 (FSN1+1) macro 388 #define FSN3 (FSN2+1) 1130 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1136 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1142 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1148 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1154 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1155 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1156 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1157 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | m10300-opc.c | 381 #define FSN2 (FSN1+1) macro 385 #define FSN3 (FSN2+1) 1127 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1133 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1139 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1145 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1151 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1152 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1153 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1154 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | m10300-opc.c | 382 #define FSN2 (FSN1+1) macro 386 #define FSN3 (FSN2+1) 1128 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1134 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1140 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1146 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1152 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1153 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1154 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1155 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | m10300-opc.c | 384 #define FSN2 (FSN1+1) macro 388 #define FSN3 (FSN2+1) 1130 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1136 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1142 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1148 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1154 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1155 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1156 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1157 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
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