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Searched refs:FSR_DZA (Results 1 – 22 of 22) sorted by relevance

/dports/math/opensolaris-libm/opensolaris-libm-2017.01.31/usr/src/libm/src/m9x/
H A Dfma.h55 #define FSR_DZA 0x40 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/riscv/
H A Dcpu_bits.h24 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) macro
26 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/
H A Dcpu_bits.h28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) macro
30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu42/qemu-4.2.1/target/riscv/
H A Dcpu_bits.h28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) macro
30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/
H A Dcpu_bits.h28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) macro
30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu5/qemu-5.2.0/target/riscv/
H A Dcpu_bits.h28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) macro
30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/riscv/
H A Dcpu_bits.h28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) macro
30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/riscv/
H A Dcpu_bits.h28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) macro
30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu/qemu-6.2.0/target/riscv/
H A Dcpu_bits.h28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) macro
30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu60/qemu-6.0.0/target/riscv/
H A Dcpu_bits.h28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) macro
30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-sparc/
H A Dcpu.h170 #define FSR_DZA (1ULL << 6) macro
172 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-sparc/
H A Dcpu.h170 #define FSR_DZA (1ULL << 6) macro
172 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu-utils/qemu-4.2.1/target/sparc/
H A Dcpu.h183 #define FSR_DZA (1ULL << 6) macro
185 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu5/qemu-5.2.0/target/sparc/
H A Dcpu.h183 #define FSR_DZA (1ULL << 6) macro
185 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/sparc/
H A Dcpu.h183 #define FSR_DZA (1ULL << 6) macro
185 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/sparc/
H A Dcpu.h168 #define FSR_DZA (1ULL << 6) macro
170 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu42/qemu-4.2.1/target/sparc/
H A Dcpu.h183 #define FSR_DZA (1ULL << 6) macro
185 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/sparc/
H A Dcpu.h183 #define FSR_DZA (1ULL << 6) macro
185 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/sparc/
H A Dcpu.h185 #define FSR_DZA (1ULL << 6) macro
187 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu/qemu-6.2.0/target/sparc/
H A Dcpu.h185 #define FSR_DZA (1ULL << 6) macro
187 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/qemu60/qemu-6.0.0/target/sparc/
H A Dcpu.h185 #define FSR_DZA (1ULL << 6) macro
187 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/
H A Ddecode.h62 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) macro
64 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)