/dports/misc/rump/buildrump.sh-b914579/src/sys/arch/sparc/include/ |
H A D | fsr.h | 54 #define FSR_RD_SHIFT 30 macro
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/riscv/ |
H A D | cpu_bits.h | 11 #define FSR_RD_SHIFT 5 macro 12 #define FSR_RD (0x7 << FSR_RD_SHIFT)
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H A D | op_helper.c | 104 env->frm = val_to_write & (FSR_RD >> FSR_RD_SHIFT); in csr_write_helper() 108 env->frm = (val_to_write & FSR_RD) >> FSR_RD_SHIFT; in csr_write_helper() 429 | (env->frm << FSR_RD_SHIFT); in csr_read_helper()
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/dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/ |
H A D | cpu_bits.h | 13 #define FSR_RD_SHIFT 5 macro 14 #define FSR_RD (0x7 << FSR_RD_SHIFT)
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H A D | csr.c | 150 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); in write_frm() 162 | (env->frm << FSR_RD_SHIFT); in read_fcsr() 174 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; in write_fcsr()
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/dports/emulators/qemu42/qemu-4.2.1/target/riscv/ |
H A D | cpu_bits.h | 13 #define FSR_RD_SHIFT 5 macro 14 #define FSR_RD (0x7 << FSR_RD_SHIFT)
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H A D | csr.c | 150 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); in write_frm() 162 | (env->frm << FSR_RD_SHIFT); in read_fcsr() 174 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; in write_fcsr()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/ |
H A D | cpu_bits.h | 13 #define FSR_RD_SHIFT 5 macro 14 #define FSR_RD (0x7 << FSR_RD_SHIFT)
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H A D | csr.c | 245 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); in write_frm() 253 | (env->frm << FSR_RD_SHIFT); in read_fcsr() 267 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; in write_fcsr()
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/dports/emulators/qemu5/qemu-5.2.0/target/riscv/ |
H A D | cpu_bits.h | 13 #define FSR_RD_SHIFT 5 macro 14 #define FSR_RD (0x7 << FSR_RD_SHIFT)
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H A D | csr.c | 213 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); in write_frm() 225 | (env->frm << FSR_RD_SHIFT); in read_fcsr() 241 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; in write_fcsr()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/riscv/ |
H A D | cpu_bits.h | 13 #define FSR_RD_SHIFT 5 macro 14 #define FSR_RD (0x7 << FSR_RD_SHIFT)
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H A D | csr.c | 164 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); in write_frm() 176 | (env->frm << FSR_RD_SHIFT); in read_fcsr() 188 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; in write_fcsr()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/riscv/ |
H A D | cpu_bits.h | 13 #define FSR_RD_SHIFT 5 macro 14 #define FSR_RD (0x7 << FSR_RD_SHIFT)
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H A D | csr.c | 174 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); in write_frm() 186 | (env->frm << FSR_RD_SHIFT); in read_fcsr() 198 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; in write_fcsr()
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/dports/emulators/qemu/qemu-6.2.0/target/riscv/ |
H A D | cpu_bits.h | 13 #define FSR_RD_SHIFT 5 macro 14 #define FSR_RD (0x7 << FSR_RD_SHIFT)
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H A D | csr.c | 255 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); in write_frm() 263 | (env->frm << FSR_RD_SHIFT); in read_fcsr() 277 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; in write_fcsr()
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/dports/emulators/qemu60/qemu-6.0.0/target/riscv/ |
H A D | cpu_bits.h | 13 #define FSR_RD_SHIFT 5 macro 14 #define FSR_RD (0x7 << FSR_RD_SHIFT)
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H A D | csr.c | 236 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); in write_frm() 248 | (env->frm << FSR_RD_SHIFT); in read_fcsr() 264 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; in write_fcsr()
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/dports/misc/rump/buildrump.sh-b914579/src/lib/libc/arch/sparc64/gen/ |
H A D | modf.S | 129 set FSR_RD_RZ << FSR_RD_SHIFT, %l4
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/dports/misc/rump/buildrump.sh-b914579/src/lib/libc/arch/sparc/gen/ |
H A D | modf.S | 134 set FSR_RD_RZ << FSR_RD_SHIFT, %l4
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/dports/emulators/mess/mame-mame0226/src/devices/cpu/sparc/ |
H A D | sparcdefs.h | 435 #define FSR_RD_SHIFT 30 macro
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/dports/emulators/mame/mame-mame0226/src/devices/cpu/sparc/ |
H A D | sparcdefs.h | 435 #define FSR_RD_SHIFT 30 macro
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/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
H A D | processor.cc | 523 csrmap[CSR_FRM] = frm = std::make_shared<float_csr_t>(proc, CSR_FRM, FSR_RD >> FSR_RD_SHIFT, 0); in reset() 525 csrmap[CSR_FCSR] = std::make_shared<composite_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT); in reset()
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H A D | decode.h | 49 #define FSR_RD_SHIFT 5 macro 50 #define FSR_RD (0x7 << FSR_RD_SHIFT)
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