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Searched refs:Fully_Constrained (Results 1 – 18 of 18) sorted by relevance

/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/
H A Dvhdl-sem_types.adb761 pragma Assert (Composite_Found or Constraint = Fully_Constrained);
767 when Fully_Constrained
788 when Fully_Constrained =>
790 return Fully_Constrained;
806 return Fully_Constrained;
886 Constraint := Fully_Constrained;
1194 if Get_Constraint_State (Type_Mark) /= Fully_Constrained then
1574 Set_Constraint_State (Res, Fully_Constrained);
2125 Constraint := Fully_Constrained;
2662 Constraint := Fully_Constrained;
H A Dvhdl-sem_assocs.adb1055 if Get_Constraint_State (Atype) /= Fully_Constrained then
1092 Get_Constraint_State (Rec_El_Type) = Fully_Constrained
1122 Set_Constraint_State (Ntype, Fully_Constrained);
1170 if Get_Constraint_State (Atype) = Fully_Constrained then
1176 Set_Constraint_State (Ntype, Fully_Constrained);
H A Dvhdl-utils.adb1043 or else Get_Constraint_State (Def) = Fully_Constrained;
1269 pragma Assert (Get_Constraint_State (Def) = Fully_Constrained);
1282 pragma Assert (Get_Constraint_State (Def) = Fully_Constrained);
H A Dvhdl-configuration.adb407 /= Fully_Constrained)
799 if Get_Constraint_State (Gen_Type) /= Fully_Constrained
H A Dvhdl-disp_tree.adb281 when Fully_Constrained =>
H A Dvhdl-sem_expr.adb2206 if Get_Constraint_State (Lit_Type) = Fully_Constrained then
3258 Constraint := Fully_Constrained;
3509 if Get_Constraint_State (Expr_Type) /= Fully_Constrained then
3947 if Get_Constraint_State (Aggr_Type) = Fully_Constrained
3965 Set_Constraint_State (A_Subtype, Fully_Constrained);
H A Dvhdl-evaluation.adb425 Set_Constraint_State (Res, Fully_Constrained);
2364 if Get_Constraint_State (Conv_Type) = Fully_Constrained then
3598 if Get_Constraint_State (Sub_Type) /= Fully_Constrained
3602 Get_Constraint_State (Val_Type) /= Fully_Constrained
H A Dvhdl-sem_utils.adb259 and then Get_Constraint_State (Type_Mark_Type) /= Fully_Constrained
H A Dvhdl-sem_names.adb855 Set_Constraint_State (Expr_Type, Fully_Constrained);
1100 and then Get_Constraint_State (Prefix_Type) = Fully_Constrained
1573 or else Get_Constraint_State (Conv_Type) = Fully_Constrained
H A Dvhdl-nodes.ads6292 Fully_Constrained literal
/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/translate/
H A Dtrans-chap7.adb76 and then Get_Constraint_State (Res_Type) = Fully_Constrained
477 if Get_Constraint_State (Str_Type) = Fully_Constrained
3559 if Get_Constraint_State (Expr_Type) = Fully_Constrained then
3581 if Get_Constraint_State (Expr_Type) = Fully_Constrained then
3656 and then Get_Constraint_State (Expr_Type) = Fully_Constrained
3944 if Get_Constraint_State (Res_Type) = Fully_Constrained then
4219 if Get_Constraint_State (Aggr_Type) /= Fully_Constrained then
H A Dtrans-chap3.adb1193 if Get_Constraint_State (Def) = Fully_Constrained then
1246 Get_Constraint_State (Def) /= Fully_Constrained;
3590 if Get_Constraint_State (L_Type) /= Fully_Constrained
3591 or else Get_Constraint_State (R_Type) /= Fully_Constrained
H A Dtrans-chap1.adb58 and then Get_Constraint_State (El_Type) /= Fully_Constrained
H A Dtrans-chap8.adb1223 elsif Get_Constraint_State (Get_Type (Expr)) /= Fully_Constrained
4465 and then Get_Constraint_State (Expr_Type) /= Fully_Constrained
4632 and then Get_Constraint_State (Target_Type) /= Fully_Constrained
4956 and then Get_Constraint_State (Target_Type) /= Fully_Constrained
H A Dtrans-rtis.adb1704 if Get_Constraint_State (Atype) = Fully_Constrained then
H A Dtrans-chap4.adb618 if Get_Constraint_State (Aggr_Type) /= Fully_Constrained then
/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/simulate/
H A Dsimul-execution.adb1727 pragma Assert (Get_Constraint_State (A_Type) = Fully_Constrained);
1806 if Get_Constraint_State (Array_Type) /= Fully_Constrained then
2246 (Get_Constraint_State (Aggregate_Type) = Fully_Constrained);
2422 if Get_Constraint_State (Target_Type) = Fully_Constrained then
3895 if Get_Constraint_State (Ref_Type) /= Fully_Constrained then
/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/libghdl/vhdl/
H A Dnodes.py1061 Fully_Constrained = 2 variable in Iir_Constraint