/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/mediatek/ |
H A D | clk-mt2701-eth.c | 19 #define GATE_ETH(_id, _name, _parent, _shift) { \ macro 29 GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), 30 GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), 31 GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), 32 GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8), 33 GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11), 34 GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14), 35 GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17), 36 GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
|
H A D | clk-mt7622-eth.c | 19 #define GATE_ETH(_id, _name, _parent, _shift) { \ macro 35 GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5), 36 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6), 37 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), 38 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), 39 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
|
H A D | clk-mt7629-eth.c | 19 #define GATE_ETH(_id, _name, _parent, _shift) { \ macro 35 GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6), 36 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), 37 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), 38 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9), 39 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
|
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/mediatek/ |
H A D | clk-mt2701-eth.c | 19 #define GATE_ETH(_id, _name, _parent, _shift) { \ macro 29 GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), 30 GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), 31 GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), 32 GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8), 33 GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11), 34 GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14), 35 GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17), 36 GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
|
H A D | clk-mt7622-eth.c | 19 #define GATE_ETH(_id, _name, _parent, _shift) { \ macro 35 GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5), 36 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6), 37 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), 38 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), 39 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
|
H A D | clk-mt7629-eth.c | 19 #define GATE_ETH(_id, _name, _parent, _shift) { \ macro 35 GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6), 36 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), 37 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), 38 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9), 39 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
|
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/mediatek/ |
H A D | clk-mt2701-eth.c | 19 #define GATE_ETH(_id, _name, _parent, _shift) { \ macro 29 GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), 30 GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), 31 GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), 32 GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8), 33 GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11), 34 GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14), 35 GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17), 36 GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
|
H A D | clk-mt7622-eth.c | 19 #define GATE_ETH(_id, _name, _parent, _shift) { \ macro 35 GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5), 36 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6), 37 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), 38 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), 39 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
|
H A D | clk-mt7629-eth.c | 19 #define GATE_ETH(_id, _name, _parent, _shift) { \ macro 35 GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6), 36 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), 37 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), 38 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9), 39 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
|
/dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 461 #define GATE_ETH(_id, _parent, _shift) { \ macro 470 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 471 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 472 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 473 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 474 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 496 #define GATE_ETH(_id, _parent, _shift) { \ macro 505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), 506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), 507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
|