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Searched refs:GATE_TOP0 (Results 1 – 25 of 183) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt7622.c70 #define GATE_TOP0(_id, _name, _parent, _shift) { \ macro
438 GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
439 GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
440 GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
442 GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
444 GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
446 GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
H A Dclk-mt2712.c960 #define GATE_TOP0(_id, _name, _parent, _shift) { \ macro
980 GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
981 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
982 GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
983 GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
984 GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
985 GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
986 GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
987 GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
H A Dclk-mt8167.c738 #define GATE_TOP0(_id, _name, _parent, _shift) { \ macro
812 GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0),
813 GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1),
814 GATE_TOP0(CLK_TOP_MFG_MM, "mfg_mm", "mfg_mm_sel", 2),
815 GATE_TOP0(CLK_TOP_SPM_52M, "spm_52m", "spm_52m_sel", 3),
817 GATE_TOP0(CLK_TOP_SCAM_MM, "scam_mm", "scam_mm_sel", 5),
818 GATE_TOP0(CLK_TOP_SMI_MM, "smi_mm", "smi_mm_sel", 9),
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt7622.c70 #define GATE_TOP0(_id, _name, _parent, _shift) { \ macro
438 GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
439 GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
440 GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
442 GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
444 GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
446 GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
H A Dclk-mt2712.c960 #define GATE_TOP0(_id, _name, _parent, _shift) { \ macro
980 GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
981 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
982 GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
983 GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
984 GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
985 GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
986 GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
987 GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
H A Dclk-mt8167.c738 #define GATE_TOP0(_id, _name, _parent, _shift) { \ macro
812 GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0),
813 GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1),
814 GATE_TOP0(CLK_TOP_MFG_MM, "mfg_mm", "mfg_mm_sel", 2),
815 GATE_TOP0(CLK_TOP_SPM_52M, "spm_52m", "spm_52m_sel", 3),
817 GATE_TOP0(CLK_TOP_SCAM_MM, "scam_mm", "scam_mm_sel", 5),
818 GATE_TOP0(CLK_TOP_SMI_MM, "smi_mm", "smi_mm_sel", 9),
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt7622.c70 #define GATE_TOP0(_id, _name, _parent, _shift) { \ macro
438 GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
439 GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
440 GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
442 GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
444 GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
446 GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
H A Dclk-mt2712.c960 #define GATE_TOP0(_id, _name, _parent, _shift) { \ macro
980 GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
981 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
982 GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
983 GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
984 GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
985 GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
986 GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
987 GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
H A Dclk-mt8167.c738 #define GATE_TOP0(_id, _name, _parent, _shift) { \ macro
812 GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0),
813 GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1),
814 GATE_TOP0(CLK_TOP_MFG_MM, "mfg_mm", "mfg_mm_sel", 2),
815 GATE_TOP0(CLK_TOP_SPM_52M, "spm_52m", "spm_52m_sel", 3),
817 GATE_TOP0(CLK_TOP_SCAM_MM, "scam_mm", "scam_mm_sel", 5),
818 GATE_TOP0(CLK_TOP_SMI_MM, "smi_mm", "smi_mm_sel", 9),
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8518.c1301 #define GATE_TOP0(_id, _parent, _shift) { \ macro
1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),

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