/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 33 #define GPC_PGC_SCU_TIMING 0x890 macro 216 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 33 #define GPC_PGC_SCU_TIMING 0x890 macro 216 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 33 #define GPC_PGC_SCU_TIMING 0x890 macro 216 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 33 #define GPC_PGC_SCU_TIMING 0x890 macro 216 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 33 #define GPC_PGC_SCU_TIMING 0x890 macro 216 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-imx/mx7/ |
H A D | soc.c | 37 #define GPC_PGC_SCU_TIMING 0x890 macro 259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
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