| /dports/games/libretro-mu/Mu-ff746b8/tools/palm/hwTestSuite/armSideCode/ |
| H A D | armControl.c | 11 return !!(PXA260_REG(PXA260_GPIO_BASE, GPLR0 + pin / 32 * 4) & 1 << pin % 32); in getGpio()
|
| H A D | armDefines.h | 29 #define GPLR0 0x0000 macro
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/drivers/pcmcia/ |
| H A D | pxa_pcmcia.c | 54 cardDetect = !(GPLR0 & GPIO_bit (14)); in pcmcia_on()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/drivers/pcmcia/ |
| H A D | pxa_pcmcia.c | 54 cardDetect = !(GPLR0 & GPIO_bit (14)); in pcmcia_on()
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/drivers/pcmcia/ |
| H A D | pxa_pcmcia.c | 54 cardDetect = !(GPLR0 & GPIO_bit (14)); in pcmcia_on()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/drivers/pcmcia/ |
| H A D | pxa_pcmcia.c | 54 cardDetect = !(GPLR0 & GPIO_bit (14)); in pcmcia_on()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/drivers/pcmcia/ |
| H A D | pxa_pcmcia.c | 54 cardDetect = !(GPLR0 & GPIO_bit (14)); in pcmcia_on()
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/drivers/pcmcia/ |
| H A D | pxa_pcmcia.c | 54 cardDetect = !(GPLR0 & GPIO_bit (14)); in pcmcia_on()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/drivers/pcmcia/ |
| H A D | pxa_pcmcia.c | 54 cardDetect = !(GPLR0 & GPIO_bit (14)); in pcmcia_on()
|
| /dports/devel/openocd/openocd-0.11.0/tcl/board/ |
| H A D | pxa255_sst.cfg | 44 mww 0x40E00000 0x000F03DB ;#GPLR0
|
| /dports/devel/openwince-include/include-0.4.2/arm/pxa2x0/ |
| H A D | gpio.h | 99 #define GPLR0 GPIO_pointer->gplr0 macro
|
| /dports/devel/codeblocks/codeblocks-20.03/src/plugins/scriptedwizard/resources/arm/files/phyCORE-PXA255/h/ |
| H A D | pxa255regs.h | 705 #define GPLR0 __REG(GPIO_BASE+0x00) /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ macro
|