/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | evergreen.c | 4337 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state() 4338 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state() 4340 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state() 4341 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state() 4344 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state() 4557 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in evergreen_irq_set() 4559 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_irq_set() 4562 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in evergreen_irq_set() 4564 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in evergreen_irq_set() 4568 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in evergreen_irq_set() [all …]
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H A D | si.c | 5695 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in si_disable_interrupt_state() 5696 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in si_disable_interrupt_state() 5699 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in si_disable_interrupt_state() 5700 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in si_disable_interrupt_state() 5703 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in si_disable_interrupt_state() 5941 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in si_irq_set() 5943 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in si_irq_set() 5947 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in si_irq_set() 5949 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in si_irq_set() 5953 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in si_irq_set() [all …]
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H A D | cik.c | 6788 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6789 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6792 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6793 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6796 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 7156 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_set() 7158 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_set() 7162 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_set() 7164 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set() 7168 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set() [all …]
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H A D | sid.h | 821 #define GRPH_INT_CONTROL 0x685c macro
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H A D | cikd.h | 896 #define GRPH_INT_CONTROL 0x685c macro
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H A D | evergreend.h | 1318 #define GRPH_INT_CONTROL 0x685c macro
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
H A D | cik.c | 6893 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6894 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6897 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6898 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6901 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 7245 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_set() 7247 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_set() 7251 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_set() 7253 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set() 7257 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set() [all …]
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H A D | sid.h | 864 #define GRPH_INT_CONTROL 0x685c macro
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H A D | cikd.h | 937 #define GRPH_INT_CONTROL 0x685c macro
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H A D | evergreend.h | 1329 #define GRPH_INT_CONTROL 0x685c macro
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H A D | evergreen.c | 4474 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in evergreen_disable_interrupt_state() 4579 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); in evergreen_irq_set()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
H A D | cik.c | 6893 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6894 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6897 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6898 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6901 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 7245 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_set() 7247 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_set() 7251 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_set() 7253 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set() 7257 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set() [all …]
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H A D | sid.h | 864 #define GRPH_INT_CONTROL 0x685c macro
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H A D | cikd.h | 937 #define GRPH_INT_CONTROL 0x685c macro
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H A D | evergreend.h | 1329 #define GRPH_INT_CONTROL 0x685c macro
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H A D | evergreen.c | 4474 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in evergreen_disable_interrupt_state() 4579 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); in evergreen_irq_set()
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H A D | si.c | 5962 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in si_disable_interrupt_state() 6120 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); in si_irq_set()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
H A D | cik.c | 6893 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6894 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6897 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6898 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6901 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 7245 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_set() 7247 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_set() 7251 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_set() 7253 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set() 7257 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set() [all …]
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H A D | sid.h | 864 #define GRPH_INT_CONTROL 0x685c macro
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H A D | cikd.h | 937 #define GRPH_INT_CONTROL 0x685c macro
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H A D | evergreend.h | 1329 #define GRPH_INT_CONTROL 0x685c macro
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H A D | evergreen.c | 4474 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in evergreen_disable_interrupt_state() 4579 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); in evergreen_irq_set()
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
H A D | sid.h | 867 #define GRPH_INT_CONTROL 0x1A17 macro
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
H A D | sid.h | 867 #define GRPH_INT_CONTROL 0x1A17 macro
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
H A D | sid.h | 867 #define GRPH_INT_CONTROL 0x1A17 macro
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