/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/ |
H A D | vhdl-configuration.adb | 151 Add_Design_Unit (Get_Design_Unit (Get_Entity (Lib_Unit)), Loc); 164 Add_Design_Unit (Get_Design_Unit (Arch), Loc); 170 Add_Design_Unit (Get_Design_Unit (Get_Entity (Lib_Unit)), Loc); 308 Entity := Get_Design_Unit (Entity_Lib); 326 Arch := Get_Design_Unit (Get_Named_Entity (Arch_Name)); 337 Arch := Get_Design_Unit (Arch); 371 (Get_Design_Unit (Get_Configuration (Aspect)), Loc); 670 Unit := Get_Design_Unit (Arch_Unit); 727 if not Get_Configuration_Mark_Flag (Get_Design_Unit (Name)) then 733 Add_Design_Unit (Get_Design_Unit (Vunit), Get_Location (Vunit)); [all …]
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H A D | vhdl-nodes_gc.adb | 343 Mark_Unit (Get_Design_Unit (Get_Named_Entity (Ent))); 354 Arch := Get_Design_Unit (Arch);
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H A D | vhdl-sem.adb | 100 (Get_Design_File (Get_Design_Unit (Library_Unit))); 149 if Get_Library (Get_Design_File (Get_Design_Unit (Entity))) /= Library 171 Entity_Unit := Get_Design_Unit (Entity_Library); 730 Entity_Unit := Get_Design_Unit (Entity); 1048 (Get_Design_Unit (Get_Entity (Father)), 1112 Design := Load_Secondary_Unit (Get_Design_Unit (Entity), 2868 Unit : constant Iir_Design_Unit := Get_Design_Unit (Pkg); 3103 (Get_Design_Unit (Pkg), Null_Identifier, Decl); 3105 Bod := Get_Design_Unit (Bod);
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H A D | vhdl-sem_specs.adb | 284 if Get_Design_Unit (Decl) /= Get_Current_Design_Unit then 1290 (Get_Design_Unit (Entity), Get_Identifier (Arch_Name)); 2021 return Get_Design_Unit (Decl);
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H A D | vhdl-canon.adb | 2349 Add_Dependence (Top, Get_Design_Unit (Get_Entity (Aspect))); 2352 Add_Dependence (Top, Get_Design_Unit (Get_Configuration (Aspect))); 3582 Set_Parent (Res, Get_Parent (Get_Design_Unit (Arch))); 3592 Add_Dependence (Res, Get_Design_Unit (Get_Entity (Config))); 3593 Add_Dependence (Res, Get_Design_Unit (Arch));
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H A D | vhdl-sem_psl.adb | 1116 Library := Get_Library (Get_Design_File (Get_Design_Unit (Unit))); 1180 Sem_Scopes.Add_Context_Clauses (Get_Design_Unit (Entity));
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H A D | vhdl-sem_scopes.adb | 1344 Add_Context_Clauses (Get_Design_Unit (Decl));
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H A D | vhdl-utils.adb | 723 return Get_Design_Unit (Get_Entity (Dep));
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H A D | vhdl-sem_types.adb | 514 P := Get_Library (Get_Design_File (Get_Design_Unit (P)));
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H A D | vhdl-nodes.ads | 8018 function Get_Design_Unit (Target : Iir) return Iir; subprogspec
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H A D | vhdl-evaluation.adb | 4216 (Get_Library (Get_Design_File (Get_Design_Unit (El))),
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H A D | vhdl-nodes.adb | 3369 function Get_Design_Unit (Target : Iir) return Iir is subprogram 3375 end Get_Design_Unit;
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/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/translate/ |
H A D | trans-chap12.adb | 144 Gen_Filename (Get_Design_File (Get_Design_Unit (Entity))); 212 Lib := Get_Library (Get_Design_File (Get_Design_Unit (Entity))); 279 Lib := Get_Library (Get_Design_File (Get_Design_Unit (Arch))); 314 Lib := Get_Library (Get_Design_File (Get_Design_Unit (Entity))); 364 Lib := Get_Library (Get_Design_File (Get_Design_Unit (Pkg))); 624 Set_Elab_Flag (Get_Design_Unit (Get_Package (Lib_Unit)), True);
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H A D | trans-chap1.adb | 176 Chap2.Elab_Dependence (Get_Design_Unit (Entity)); 361 Chap2.Elab_Dependence (Get_Design_Unit (Arch)); 954 Chap2.Elab_Dependence (Get_Design_Unit (Config));
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H A D | trans-chap2.adb | 1016 Elab_Dependence (Get_Design_Unit (Spec)); 1091 Elab_Dependence (Get_Design_Unit (Bod)); 1611 Elab_Dependence (Get_Design_Unit (Inst));
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H A D | trans-chap9.adb | 1954 Entity_Unit := Get_Design_Unit (Entity);
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H A D | trans-rtis.adb | 2912 (Get_Design_Unit (Lib_Unit)));
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H A D | trans-chap8.adb | 1301 Get_Design_File (Get_Design_Unit (Current_Library_Unit));
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/dports/cad/ghdl/ghdl-1.0.0/src/synth/ |
H A D | synth-insts.adb | 1236 Bod_Unit := Get_Design_Unit (Bod); 1277 Synth_Dependencies (Global_Instance, Get_Design_Unit (Entity)); 1278 Synth_Dependencies (Global_Instance, Get_Design_Unit (Arch)); 1498 Synth_Dependencies (Root_Instance, Get_Design_Unit (Arch));
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H A D | synth-disp_vhdl.adb | 415 Unit : constant Node := Get_Design_Unit (Ent);
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H A D | synth-expr.adb | 1763 (Get_Library (Get_Design_File (Get_Design_Unit (Parent))))
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/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/simulate/ |
H A D | simul-debugger.adb | 1756 Unit : constant Iir := Get_Design_Unit (N); 1764 Add_Context_Clauses (Get_Design_Unit (N)); 1770 Package_Unit : constant Iir := Get_Design_Unit (Package_Decl);
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H A D | simul-elaboration.adb | 500 Design := Get_Design_Unit (Library_Unit); 2095 (Get_Design_Unit (Entity), Arch_Name, Stmt); 2847 Elaborate_Dependence (Get_Design_Unit (Arch)); 3040 Arch_Unit := Get_Design_Unit (Arch);
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/dports/cad/ghdl/ghdl-1.0.0/src/ |
H A D | libraries.adb | 897 (Get_Design_Unit (Get_Entity (Unit)), 1529 Lib := Get_Library (Get_Design_File (Get_Design_Unit (Entity)));
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/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/libghdl/vhdl/ |
H A D | nodes.py | 2107 Get_Design_Unit = libghdl.vhdl__nodes__get_design_unit variable
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