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Searched refs:Get_Port_Chain (Results 1 – 25 of 29) sorted by relevance

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/dports/cad/ghdl/ghdl-1.0.0/src/synth/
H A Dsynth-insts.adb131 Inter := Get_Port_Chain (Params.Decl);
237 Ports : constant Node := Get_Port_Chain (Decl);
425 Inter := Get_Port_Chain (Decl);
493 Inter := Get_Port_Chain (Decl);
812 Assoc_Inter := Get_Port_Chain (Inst_Obj.Decl);
939 Get_Port_Chain (Ent),
1090 Assoc_Inter := Get_Port_Chain (Component);
1143 Get_Port_Chain (Ent),
1179 Assoc_Inter := Get_Port_Chain (Component);
1304 Inter := Get_Port_Chain (Entity);
[all …]
H A Dsynth-disp_vhdl.adb492 Port := Get_Port_Chain (Ent);
500 Port := Get_Port_Chain (Ent);
H A Dsynth-debugger__on.adb769 or else Walk_Decl_Chain (Get_Port_Chain (Unit)) = Walk_Abort
/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/simulate/
H A Dsimul-elaboration.adb1439 Elaborate_Port_Clause (Instance, Get_Port_Chain (Header));
1442 Get_Port_Chain (Header), Get_Port_Map_Aspect_Chain (Header));
1655 Elaborate_Port_Clause (Frame, Get_Port_Chain (Component));
1658 Get_Port_Chain (Component), Get_Port_Map_Aspect_Chain (Stmt));
2120 Create_Default_Association (Get_Port_Chain (Entity),
2121 Get_Port_Chain (Component),
2852 Elaborate_Port_Clause (Instance, Get_Port_Chain (Entity));
2854 Get_Port_Chain (Entity), Port_Map);
3054 (Get_Port_Chain (Entity), Null_Iir, Entity);
3058 Check_No_Unconstrained (Get_Port_Chain (Entity), Port_Map);
H A Dsimul-debugger.adb502 (Instance, Get_Port_Chain (Ent));
517 (Instance, Get_Port_Chain (Header));
535 (Instance, Get_Port_Chain (Instance.Stmt));
642 (Instance, Get_Port_Chain (Entity));
935 or else Walk_Decl_Chain (Get_Port_Chain (Unit)) = Walk_Abort
1634 (Get_Port_Chain (Decl), Instance);
1804 Add_Declarations (Get_Port_Chain (Header), False);
/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/dom/
H A DDesignUnit.py79 return pyutils.chain_iter(nodes.Get_Port_Chain(entity))
/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/
H A Dvhdl-configuration.adb428 Inter_Chain : constant Iir := Get_Port_Chain (Ent);
479 Inst_Inter_Chain := Get_Port_Chain (Comp);
847 El := Get_Port_Chain (Entity);
H A Dvhdl-sem_specs.adb652 Sem_Named_Entity_Chain (Get_Port_Chain (Scope));
659 Sem_Named_Entity_Chain (Get_Port_Chain (Header));
1914 Ent_Chain := Get_Port_Chain (Entity);
1915 Comp_Chain := Get_Port_Chain (Comp);
H A Dvhdl-annotations.adb567 Annotate_Interface_List (Info, Get_Port_Chain (Comp), True);
928 Annotate_Interface_List (Info, Get_Port_Chain (Header), True);
1102 Annotate_Interface_List (Entity_Info, Get_Port_Chain (Decl), True);
H A Dvhdl-canon.adb2063 (Get_Port_Chain (Inst),
2102 (Get_Port_Chain (Header), Chain, Chain);
2105 (Get_Port_Chain (Header));
2437 (Get_Port_Chain (Entity), Map_Chain, Map_Chain);
2630 Merge_Association_Chain (Get_Port_Chain (Entity),
3496 Canon_Interface_List (Get_Port_Chain (El));
H A Dvhdl-sem.adb80 Sem_Interface_Chain (Get_Port_Chain (Entity), Port_Interface_List);
655 Inter_Chain := Get_Port_Chain (Inter_Parent);
686 Inter := Get_Port_Chain (Inter_Parent);
1204 Inter_Chain : constant Iir := Get_Port_Chain (Comp);
H A Dvhdl-sem_scopes.adb1281 Add_Declarations_From_Interface_Chain (Get_Port_Chain (Entity));
1331 Add_Declarations_From_Interface_Chain (Get_Port_Chain (Component));
H A Dvhdl-ieee-vital_timing.adb1273 Decl := Get_Port_Chain (Ent);
H A Dvhdl-sem_names.adb399 Iterator_Decl_Chain (Get_Port_Chain (Decl), Id);
426 Iterator_Decl_Chain (Get_Port_Chain (Header), Id);
H A Dvhdl-sem_decls.adb1378 (Get_Port_Chain (Component), Port_Interface_List);
H A Dvhdl-prints.adb1293 Ports : constant Iir := Get_Port_Chain (Parent);
1360 if Get_Port_Chain (Decl) /= Null_Iir then
3714 Chain := Get_Port_Chain (Header);
H A Dvhdl-sem_stmts.adb2016 Port_Chain := Get_Port_Chain (Header);
/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/libghdl/
H A Dutils.py188 for n1 in chain_iter(nodes.Get_Port_Chain(n)):
/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/lsp/
H A Dworkspace.py475 "ports": create_interfaces(nodes.Get_Port_Chain(ent)),
/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/translate/
H A Dtrans-chap9.adb201 Inter := Get_Port_Chain (Ports);
2701 Merge_Signals_Rti_Of_Port_Chain (Get_Port_Chain (Block));
2722 Merge_Signals_Rti_Of_Port_Chain (Get_Port_Chain (Header));
H A Dtrans-rtis.adb2098 (Get_Port_Chain (Comp), Info.Comp_Rti_Const);
2668 Generate_Declaration_Chain (Get_Port_Chain (Blk), Rti);
2692 Generate_Declaration_Chain (Get_Port_Chain (Header), Rti);
H A Dtrans-chap5.adb705 Inter := Get_Port_Chain (Header);
H A Dtrans-chap1.adb84 El := Get_Port_Chain (Entity);
H A Dtrans-chap4.adb1790 Port := Get_Port_Chain (Parent);
3109 Inter := Get_Port_Chain (Stmt);
3111 Inter := Get_Port_Chain (Entity);
/dports/cad/ghdl/ghdl-1.0.0/src/ghdldrv/
H A Dghdllocal.adb692 if Get_Port_Chain (Unit) /= Null_Iir then

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