/dports/cad/ghdl/ghdl-1.0.0/src/synth/ |
H A D | synth-insts.adb | 131 Inter := Get_Port_Chain (Params.Decl); 237 Ports : constant Node := Get_Port_Chain (Decl); 425 Inter := Get_Port_Chain (Decl); 493 Inter := Get_Port_Chain (Decl); 812 Assoc_Inter := Get_Port_Chain (Inst_Obj.Decl); 939 Get_Port_Chain (Ent), 1090 Assoc_Inter := Get_Port_Chain (Component); 1143 Get_Port_Chain (Ent), 1179 Assoc_Inter := Get_Port_Chain (Component); 1304 Inter := Get_Port_Chain (Entity); [all …]
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H A D | synth-disp_vhdl.adb | 492 Port := Get_Port_Chain (Ent); 500 Port := Get_Port_Chain (Ent);
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H A D | synth-debugger__on.adb | 769 or else Walk_Decl_Chain (Get_Port_Chain (Unit)) = Walk_Abort
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/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/simulate/ |
H A D | simul-elaboration.adb | 1439 Elaborate_Port_Clause (Instance, Get_Port_Chain (Header)); 1442 Get_Port_Chain (Header), Get_Port_Map_Aspect_Chain (Header)); 1655 Elaborate_Port_Clause (Frame, Get_Port_Chain (Component)); 1658 Get_Port_Chain (Component), Get_Port_Map_Aspect_Chain (Stmt)); 2120 Create_Default_Association (Get_Port_Chain (Entity), 2121 Get_Port_Chain (Component), 2852 Elaborate_Port_Clause (Instance, Get_Port_Chain (Entity)); 2854 Get_Port_Chain (Entity), Port_Map); 3054 (Get_Port_Chain (Entity), Null_Iir, Entity); 3058 Check_No_Unconstrained (Get_Port_Chain (Entity), Port_Map);
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H A D | simul-debugger.adb | 502 (Instance, Get_Port_Chain (Ent)); 517 (Instance, Get_Port_Chain (Header)); 535 (Instance, Get_Port_Chain (Instance.Stmt)); 642 (Instance, Get_Port_Chain (Entity)); 935 or else Walk_Decl_Chain (Get_Port_Chain (Unit)) = Walk_Abort 1634 (Get_Port_Chain (Decl), Instance); 1804 Add_Declarations (Get_Port_Chain (Header), False);
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/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/dom/ |
H A D | DesignUnit.py | 79 return pyutils.chain_iter(nodes.Get_Port_Chain(entity))
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/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/ |
H A D | vhdl-configuration.adb | 428 Inter_Chain : constant Iir := Get_Port_Chain (Ent); 479 Inst_Inter_Chain := Get_Port_Chain (Comp); 847 El := Get_Port_Chain (Entity);
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H A D | vhdl-sem_specs.adb | 652 Sem_Named_Entity_Chain (Get_Port_Chain (Scope)); 659 Sem_Named_Entity_Chain (Get_Port_Chain (Header)); 1914 Ent_Chain := Get_Port_Chain (Entity); 1915 Comp_Chain := Get_Port_Chain (Comp);
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H A D | vhdl-annotations.adb | 567 Annotate_Interface_List (Info, Get_Port_Chain (Comp), True); 928 Annotate_Interface_List (Info, Get_Port_Chain (Header), True); 1102 Annotate_Interface_List (Entity_Info, Get_Port_Chain (Decl), True);
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H A D | vhdl-canon.adb | 2063 (Get_Port_Chain (Inst), 2102 (Get_Port_Chain (Header), Chain, Chain); 2105 (Get_Port_Chain (Header)); 2437 (Get_Port_Chain (Entity), Map_Chain, Map_Chain); 2630 Merge_Association_Chain (Get_Port_Chain (Entity), 3496 Canon_Interface_List (Get_Port_Chain (El));
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H A D | vhdl-sem.adb | 80 Sem_Interface_Chain (Get_Port_Chain (Entity), Port_Interface_List); 655 Inter_Chain := Get_Port_Chain (Inter_Parent); 686 Inter := Get_Port_Chain (Inter_Parent); 1204 Inter_Chain : constant Iir := Get_Port_Chain (Comp);
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H A D | vhdl-sem_scopes.adb | 1281 Add_Declarations_From_Interface_Chain (Get_Port_Chain (Entity)); 1331 Add_Declarations_From_Interface_Chain (Get_Port_Chain (Component));
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H A D | vhdl-ieee-vital_timing.adb | 1273 Decl := Get_Port_Chain (Ent);
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H A D | vhdl-sem_names.adb | 399 Iterator_Decl_Chain (Get_Port_Chain (Decl), Id); 426 Iterator_Decl_Chain (Get_Port_Chain (Header), Id);
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H A D | vhdl-sem_decls.adb | 1378 (Get_Port_Chain (Component), Port_Interface_List);
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H A D | vhdl-prints.adb | 1293 Ports : constant Iir := Get_Port_Chain (Parent); 1360 if Get_Port_Chain (Decl) /= Null_Iir then 3714 Chain := Get_Port_Chain (Header);
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H A D | vhdl-sem_stmts.adb | 2016 Port_Chain := Get_Port_Chain (Header);
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/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/libghdl/ |
H A D | utils.py | 188 for n1 in chain_iter(nodes.Get_Port_Chain(n)):
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/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/lsp/ |
H A D | workspace.py | 475 "ports": create_interfaces(nodes.Get_Port_Chain(ent)),
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/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/translate/ |
H A D | trans-chap9.adb | 201 Inter := Get_Port_Chain (Ports); 2701 Merge_Signals_Rti_Of_Port_Chain (Get_Port_Chain (Block)); 2722 Merge_Signals_Rti_Of_Port_Chain (Get_Port_Chain (Header));
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H A D | trans-rtis.adb | 2098 (Get_Port_Chain (Comp), Info.Comp_Rti_Const); 2668 Generate_Declaration_Chain (Get_Port_Chain (Blk), Rti); 2692 Generate_Declaration_Chain (Get_Port_Chain (Header), Rti);
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H A D | trans-chap5.adb | 705 Inter := Get_Port_Chain (Header);
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H A D | trans-chap1.adb | 84 El := Get_Port_Chain (Entity);
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H A D | trans-chap4.adb | 1790 Port := Get_Port_Chain (Parent); 3109 Inter := Get_Port_Chain (Stmt); 3111 Inter := Get_Port_Chain (Entity);
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/dports/cad/ghdl/ghdl-1.0.0/src/ghdldrv/ |
H A D | ghdllocal.adb | 692 if Get_Port_Chain (Unit) /= Null_Iir then
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