/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/ |
H A D | vhdl-utils.adb | 1394 if Get_Base_Type (Get_Return_Type (L1)) /= 1395 Get_Base_Type (Get_Return_Type (R1)) 1411 and then Get_Base_Type (Get_Return_Type (R1)) = Get_Type (L1); 1416 and then Get_Base_Type (Get_Return_Type (L1)) = Get_Type (R1); 1455 and then Get_Base_Type (Get_Return_Type (Subprg)) = Base_Type
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H A D | vhdl-sem_expr.adb | 1276 or else (Compatibility_Nodes (A_Type, Get_Return_Type (A_Func)) 1318 Set_Type (Expr, Get_Return_Type (Inter)); 1347 (Res_Type, Get_Return_Type (Get_Element (Imp_It))); 1440 Set_Type (Expr, Get_Return_Type (Inter_List)); 1469 (A_Type, Get_Base_Type (Get_Return_Type (Inter))) 1486 (A_Type, Get_Base_Type (Get_Return_Type (Inter_List))) 1514 Set_Type (Expr, Get_Return_Type (Res)); 1643 if Get_Base_Type (Get_Return_Type (El)) /= Boolean_Type_Definition 1734 Set_Type (Expr, Get_Return_Type (Decl)); 1837 Res := Are_Types_Compatible (Res_Type, Get_Return_Type (Decl)); [all …]
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H A D | vhdl-errors.adb | 976 Append_Type (Get_Return_Type (Subprg));
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H A D | vhdl-sem_names.adb | 164 Add_Element (Res_List, Get_Return_Type (Decl)); 594 Set_Type (Call, Get_Return_Type (Spec)); 1890 Set_Type (Name_Res, Get_Return_Type (Res)); 2517 Error_Selected_Element (Get_Return_Type (Prefix));
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H A D | vhdl-sem_stmts.adb | 1099 Set_Type (Stmt, Get_Return_Type (Current_Subprogram)); 1100 Expr := Sem_Expression (Expr, Get_Return_Type (Current_Subprogram));
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H A D | vhdl-sem_utils.adb | 45 Itype := Get_Base_Type (Get_Return_Type (Subprg));
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H A D | vhdl-sem.adb | 1417 if not Are_Trees_Equal (Get_Return_Type (Left), 1418 Get_Return_Type (Right))
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H A D | vhdl-sem_types.adb | 631 Inter_Type := Get_Return_Type (El); 1345 Ret_Type := Get_Return_Type (Func);
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H A D | vhdl-annotations.adb | 515 (Block_Info, Get_Return_Type (Subprg));
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H A D | vhdl-nodes.ads | 7972 function Get_Return_Type (Target : Iir) return Iir; subprogspec 7974 pragma Inline (Get_Return_Type);
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H A D | vhdl-sem_decls.adb | 1492 Get_Base_Type (Get_Return_Type (N_Entity))
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H A D | vhdl-sem_assocs.adb | 1593 if (Get_Base_Type (Get_Return_Type (Decl))
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H A D | vhdl-evaluation.adb | 1230 Get_Return_Type (Get_Implementation (Orig));
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H A D | vhdl-nodes.adb | 3255 function Get_Return_Type (Target : Iir) return Iir is subprogram 3261 end Get_Return_Type;
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H A D | vhdl-prints.adb | 1711 Get_Return_Type (Subprg)));
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H A D | vhdl-nodes_meta.adb | 6125 return Get_Return_Type (N);
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/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/translate/ |
H A D | trans-chap7.adb | 787 (Res, Get_Return_Type (Imp), Res_Type, Mode_Value, Left); 1126 Rtype := Get_Return_Type (Imp); 1205 Info : constant Type_Info_Acc := Get_Info (Get_Return_Type (Func)); 1228 Ret_Type : constant Iir := Get_Return_Type (Func); 1245 Expr_Type : constant Iir := Get_Return_Type (Concat_Imp); 1278 and then Get_Return_Type (Imp) = Expr_Type 1290 and then Get_Return_Type (Imp) = Expr_Type 2362 (Res, Get_Return_Type (Imp), Res_Type, Mode_Value, Expr); 4437 Expr_Type := Get_Return_Type (Imp);
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H A D | trans-chap2.adb | 262 Rtype := Get_Return_Type (Spec); 668 Get_Ortho_Type (Get_Return_Type (Spec), Mode_Value));
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H A D | trans-chap4.adb | 2142 Ret_Type := Get_Return_Type (Func); 3001 Res_Type : constant Iir := Get_Return_Type (Func); 3042 (Chap7.Translate_Implicit_Conv (E, Get_Return_Type (Func),
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H A D | trans-chap8.adb | 208 Ret_Type := Get_Return_Type (Chap2.Current_Subprogram); 2761 Res_Otype := Get_Info (Get_Return_Type (Imp)); 3374 Res_Type : constant Iir := Get_Return_Type (Imp);
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/dports/cad/ghdl/ghdl-1.0.0/src/synth/ |
H A D | synth-stmts.adb | 1949 C.Ret_Typ := Get_Subtype_Object (Syn_Inst, Get_Return_Type (Imp)); 2037 C.Ret_Typ := Get_Subtype_Object (Syn_Inst, Get_Return_Type (Imp));
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/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/simulate/ |
H A D | simul-execution.adb | 1275 Get_Return_Type (Get_Implementation (Expr)); 1289 Get_Return_Type (Get_Implementation (Expr));
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/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/libghdl/vhdl/ |
H A D | nodes.py | 2086 Get_Return_Type = libghdl.vhdl__nodes__get_return_type variable
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