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Searched refs:HIFN_1_DMA_CSR (Results 1 – 5 of 5) sorted by relevance

/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/pci/
H A Dhifn7751.c1043 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1280 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1323 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1345 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1388 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1804 READ_REG_1(sc, HIFN_1_DMA_CSR),
1854 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1882 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1982 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
2002 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
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H A Dhifn7751reg.h192 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/crypto/
H A Dhifn_795x.c174 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ macro
674 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_stop_device()
994 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1008 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1022 hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_init_registers()
1222 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); in hifn_setup_cmd_desc()
1258 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); in hifn_setup_src_desc()
1285 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); in hifn_setup_res_desc()
1806 hifn_write_1(dev, HIFN_1_DMA_CSR, r); in hifn_work()
1855 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_interrupt()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/crypto/
H A Dhifn_795x.c174 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ macro
674 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_stop_device()
994 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1008 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1022 hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_init_registers()
1222 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); in hifn_setup_cmd_desc()
1258 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); in hifn_setup_src_desc()
1285 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); in hifn_setup_res_desc()
1806 hifn_write_1(dev, HIFN_1_DMA_CSR, r); in hifn_work()
1855 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_interrupt()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/crypto/
H A Dhifn_795x.c174 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ macro
674 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_stop_device()
994 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1008 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1022 hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_init_registers()
1222 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); in hifn_setup_cmd_desc()
1258 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); in hifn_setup_src_desc()
1285 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); in hifn_setup_res_desc()
1806 hifn_write_1(dev, HIFN_1_DMA_CSR, r); in hifn_work()
1855 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_interrupt()
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