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Searched refs:HOSTCC_STATUS_BLK_HOST_ADDR (Results 1 – 24 of 24) sorted by relevance

/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_hw.c1847 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
1849 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
H A Dtg3.h1356 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_hw.c1847 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
1849 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
H A Dtg3.h1356 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_hw.c1847 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
1849 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
H A Dtg3.h1356 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_hw.c1847 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
1849 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
H A Dtg3.h1356 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_hw.c1847 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
1849 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
H A Dtg3.h1343 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_hw.c1847 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
1849 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
H A Dtg3.h1356 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
/dports/net/ipxe/ipxe-2265a65/src/drivers/net/tg3/
H A Dtg3_hw.c1847 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
1849 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
H A Dtg3.h1356 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_hw.c1847 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
1849 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
H A Dtg3.h1356 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
/dports/sysutils/syslinux/syslinux-6.03/gpxe/src/drivers/net/
H A Dtg3.h909 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
H A Dtg3.c2173 HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0, in tg3_setup_hw()
2216 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_setup_hw()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/broadcom/
H A Dtg3.h1275 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
H A Dtg3.c9641 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
9643 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
13189 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, in tg3_test_registers()
13191 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, in tg3_test_registers()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/broadcom/
H A Dtg3.h1275 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
H A Dtg3.c9641 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
9643 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
13189 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, in tg3_test_registers()
13191 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, in tg3_test_registers()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/broadcom/
H A Dtg3.h1275 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ macro
H A Dtg3.c9641 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
9643 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
13189 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, in tg3_test_registers()
13191 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, in tg3_test_registers()