| /dports/devel/py-keystone-engine/keystone-engine-0.9.1-3/src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenRegisterInfo.inc | 678 …Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon…
688 …Hexagon::LC0, Hexagon::SA0, Hexagon::LC1, Hexagon::SA1, Hexagon::P3_0, Hexagon::M0, Hexagon::M1, H…
698 …Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon…
708 Hexagon::P0, Hexagon::P1, Hexagon::P2, Hexagon::P3,
738 …Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D4, Hexagon::D6, Hexagon::D7, Hexagon…
748 …Hexagon::C1_0, Hexagon::C3_2, Hexagon::C7_6, Hexagon::C9_8, Hexagon::C11_10, Hexagon::CS, Hexagon:…
758 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
778 …Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon…
798 …Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon…
808 …Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon…
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
|
| H A D | HexagonInstrInfo.cpp | 128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
1013 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); in expandPostRAPseudo()
3451 {Hexagon::A2_add, Hexagon::dup_A2_add}, in getDuplexOpcode()
3452 {Hexagon::A2_addi, Hexagon::dup_A2_addi}, in getDuplexOpcode()
3453 {Hexagon::A2_andir, Hexagon::dup_A2_andir}, in getDuplexOpcode()
3455 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb}, in getDuplexOpcode()
3456 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth}, in getDuplexOpcode()
3457 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr}, in getDuplexOpcode()
3459 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb}, in getDuplexOpcode()
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
|
| H A D | HexagonInstrInfo.cpp | 128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
1013 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); in expandPostRAPseudo()
3451 {Hexagon::A2_add, Hexagon::dup_A2_add}, in getDuplexOpcode()
3452 {Hexagon::A2_addi, Hexagon::dup_A2_addi}, in getDuplexOpcode()
3453 {Hexagon::A2_andir, Hexagon::dup_A2_andir}, in getDuplexOpcode()
3455 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb}, in getDuplexOpcode()
3456 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth}, in getDuplexOpcode()
3457 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr}, in getDuplexOpcode()
3459 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb}, in getDuplexOpcode()
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
|
| H A D | HexagonInstrInfo.cpp | 128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
1013 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); in expandPostRAPseudo()
3451 {Hexagon::A2_add, Hexagon::dup_A2_add}, in getDuplexOpcode()
3452 {Hexagon::A2_addi, Hexagon::dup_A2_addi}, in getDuplexOpcode()
3453 {Hexagon::A2_andir, Hexagon::dup_A2_andir}, in getDuplexOpcode()
3455 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb}, in getDuplexOpcode()
3456 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth}, in getDuplexOpcode()
3457 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr}, in getDuplexOpcode()
3459 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb}, in getDuplexOpcode()
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
|
| H A D | HexagonInstrInfo.cpp | 128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
1013 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); in expandPostRAPseudo()
3451 {Hexagon::A2_add, Hexagon::dup_A2_add}, in getDuplexOpcode()
3452 {Hexagon::A2_addi, Hexagon::dup_A2_addi}, in getDuplexOpcode()
3453 {Hexagon::A2_andir, Hexagon::dup_A2_andir}, in getDuplexOpcode()
3455 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb}, in getDuplexOpcode()
3456 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth}, in getDuplexOpcode()
3457 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr}, in getDuplexOpcode()
3459 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb}, in getDuplexOpcode()
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
|
| H A D | HexagonInstrInfo.cpp | 128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
1013 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); in expandPostRAPseudo()
3451 {Hexagon::A2_add, Hexagon::dup_A2_add}, in getDuplexOpcode()
3452 {Hexagon::A2_addi, Hexagon::dup_A2_addi}, in getDuplexOpcode()
3453 {Hexagon::A2_andir, Hexagon::dup_A2_andir}, in getDuplexOpcode()
3455 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb}, in getDuplexOpcode()
3456 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth}, in getDuplexOpcode()
3457 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr}, in getDuplexOpcode()
3459 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb}, in getDuplexOpcode()
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
|
| H A D | HexagonInstrInfo.cpp | 128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
1013 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); in expandPostRAPseudo()
3451 {Hexagon::A2_add, Hexagon::dup_A2_add}, in getDuplexOpcode()
3452 {Hexagon::A2_addi, Hexagon::dup_A2_addi}, in getDuplexOpcode()
3453 {Hexagon::A2_andir, Hexagon::dup_A2_andir}, in getDuplexOpcode()
3455 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb}, in getDuplexOpcode()
3456 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth}, in getDuplexOpcode()
3457 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr}, in getDuplexOpcode()
3459 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb}, in getDuplexOpcode()
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
|
| H A D | HexagonInstrInfo.cpp | 128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
1013 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); in expandPostRAPseudo()
3451 {Hexagon::A2_add, Hexagon::dup_A2_add}, in getDuplexOpcode()
3452 {Hexagon::A2_addi, Hexagon::dup_A2_addi}, in getDuplexOpcode()
3453 {Hexagon::A2_andir, Hexagon::dup_A2_andir}, in getDuplexOpcode()
3455 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb}, in getDuplexOpcode()
3456 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth}, in getDuplexOpcode()
3457 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr}, in getDuplexOpcode()
3459 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb}, in getDuplexOpcode()
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6:
22 case Hexagon::Sched::tc_151bf368:
23 case Hexagon::Sched::tc_1c2c7a4a:
24 case Hexagon::Sched::tc_1d41f8b7:
25 case Hexagon::Sched::tc_23708a21:
26 case Hexagon::Sched::tc_24f426ab:
27 case Hexagon::Sched::tc_2f573607:
28 case Hexagon::Sched::tc_388f9897:
29 case Hexagon::Sched::tc_3d14a17b:
30 case Hexagon::Sched::tc_3fbf1042:
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_05d3a09b: in is_TC3x()
22 case Hexagon::Sched::tc_0d8f5752: in is_TC3x()
23 case Hexagon::Sched::tc_13bfbcf9: in is_TC3x()
24 case Hexagon::Sched::tc_174516e8: in is_TC3x()
25 case Hexagon::Sched::tc_1a2fd869: in is_TC3x()
26 case Hexagon::Sched::tc_1c4528a2: in is_TC3x()
27 case Hexagon::Sched::tc_32779c6f: in is_TC3x()
28 case Hexagon::Sched::tc_5b54b33f: in is_TC3x()
29 case Hexagon::Sched::tc_6b25e783: in is_TC3x()
30 case Hexagon::Sched::tc_76851da1: in is_TC3x()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_05d3a09b: in is_TC3x()
22 case Hexagon::Sched::tc_0d8f5752: in is_TC3x()
23 case Hexagon::Sched::tc_13bfbcf9: in is_TC3x()
24 case Hexagon::Sched::tc_174516e8: in is_TC3x()
25 case Hexagon::Sched::tc_1a2fd869: in is_TC3x()
26 case Hexagon::Sched::tc_1c4528a2: in is_TC3x()
27 case Hexagon::Sched::tc_32779c6f: in is_TC3x()
28 case Hexagon::Sched::tc_5b54b33f: in is_TC3x()
29 case Hexagon::Sched::tc_6b25e783: in is_TC3x()
30 case Hexagon::Sched::tc_76851da1: in is_TC3x()
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_05d3a09b: in is_TC3x()
22 case Hexagon::Sched::tc_0d8f5752: in is_TC3x()
23 case Hexagon::Sched::tc_13bfbcf9: in is_TC3x()
24 case Hexagon::Sched::tc_174516e8: in is_TC3x()
25 case Hexagon::Sched::tc_1a2fd869: in is_TC3x()
26 case Hexagon::Sched::tc_1c4528a2: in is_TC3x()
27 case Hexagon::Sched::tc_32779c6f: in is_TC3x()
28 case Hexagon::Sched::tc_5b54b33f: in is_TC3x()
29 case Hexagon::Sched::tc_6b25e783: in is_TC3x()
30 case Hexagon::Sched::tc_76851da1: in is_TC3x()
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_05d3a09b: in is_TC3x()
22 case Hexagon::Sched::tc_0d8f5752: in is_TC3x()
23 case Hexagon::Sched::tc_13bfbcf9: in is_TC3x()
24 case Hexagon::Sched::tc_174516e8: in is_TC3x()
25 case Hexagon::Sched::tc_1a2fd869: in is_TC3x()
26 case Hexagon::Sched::tc_1c4528a2: in is_TC3x()
27 case Hexagon::Sched::tc_32779c6f: in is_TC3x()
28 case Hexagon::Sched::tc_5b54b33f: in is_TC3x()
29 case Hexagon::Sched::tc_6b25e783: in is_TC3x()
30 case Hexagon::Sched::tc_76851da1: in is_TC3x()
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 22 case Hexagon::Sched::tc_05d3a09b: in is_TC3x()
23 case Hexagon::Sched::tc_0d8f5752: in is_TC3x()
24 case Hexagon::Sched::tc_13bfbcf9: in is_TC3x()
25 case Hexagon::Sched::tc_174516e8: in is_TC3x()
26 case Hexagon::Sched::tc_1a2fd869: in is_TC3x()
27 case Hexagon::Sched::tc_1c4528a2: in is_TC3x()
28 case Hexagon::Sched::tc_32779c6f: in is_TC3x()
29 case Hexagon::Sched::tc_5b54b33f: in is_TC3x()
30 case Hexagon::Sched::tc_6b25e783: in is_TC3x()
31 case Hexagon::Sched::tc_76851da1: in is_TC3x()
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 23 case Hexagon::Sched::tc_16d0d8d5: in is_TC3x()
24 case Hexagon::Sched::tc_1853ea6d: in is_TC3x()
25 case Hexagon::Sched::tc_60571023: in is_TC3x()
26 case Hexagon::Sched::tc_7934b9df: in is_TC3x()
27 case Hexagon::Sched::tc_8fd5f294: in is_TC3x()
28 case Hexagon::Sched::tc_b9c0b731: in is_TC3x()
29 case Hexagon::Sched::tc_bcc96cee: in is_TC3x()
30 case Hexagon::Sched::tc_c6ce9b3f: in is_TC3x()
31 case Hexagon::Sched::tc_c6ebf8dd: in is_TC3x()
32 case Hexagon::Sched::tc_c82dc1ff: in is_TC3x()
[all …]
|