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Searched refs:ICC_CTLR_EL1_EOIMODE (Results 1 – 18 of 18) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/hw/intc/
H A Darm_gicv3_cpuif.c568 value |= ICC_CTLR_EL1_EOIMODE; in icv_ctlr_read()
589 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); in icv_ctlr_write()
1067 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1069 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1817 mask = ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1819 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1834 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1840 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1862 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
1868 cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
[all …]
H A Dgicv3_internal.h138 #define ICC_CTLR_EL1_EOIMODE (1U << 1) macro
/dports/emulators/qemu/qemu-6.2.0/hw/intc/
H A Darm_gicv3_cpuif.c572 value |= ICC_CTLR_EL1_EOIMODE; in icv_ctlr_read()
593 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); in icv_ctlr_write()
1076 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1078 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1844 mask = ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1846 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1861 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1867 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1889 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
1895 cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
[all …]
H A Dgicv3_internal.h146 #define ICC_CTLR_EL1_EOIMODE (1U << 1) macro
/dports/emulators/qemu60/qemu-6.0.0/hw/intc/
H A Darm_gicv3_cpuif.c569 value |= ICC_CTLR_EL1_EOIMODE; in icv_ctlr_read()
590 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); in icv_ctlr_write()
1071 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1073 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1821 mask = ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1823 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1838 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1844 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1866 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
1872 cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
[all …]
H A Dgicv3_internal.h138 #define ICC_CTLR_EL1_EOIMODE (1U << 1) macro
/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/
H A Darm_gicv3_cpuif.c568 value |= ICC_CTLR_EL1_EOIMODE; in icv_ctlr_read()
589 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); in icv_ctlr_write()
1067 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1069 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1817 mask = ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1819 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1834 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1840 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1862 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
1868 cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
[all …]
H A Dgicv3_internal.h138 #define ICC_CTLR_EL1_EOIMODE (1U << 1) macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/
H A Darm_gicv3_cpuif.c567 value |= ICC_CTLR_EL1_EOIMODE; in icv_ctlr_read()
588 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); in icv_ctlr_write()
1066 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1068 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1815 mask = ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1817 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1832 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1838 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1860 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
1866 cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
[all …]
H A Dgicv3_internal.h138 #define ICC_CTLR_EL1_EOIMODE (1U << 1) macro
/dports/emulators/qemu5/qemu-5.2.0/hw/intc/
H A Darm_gicv3_cpuif.c569 value |= ICC_CTLR_EL1_EOIMODE; in icv_ctlr_read()
590 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); in icv_ctlr_write()
1071 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1073 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1821 mask = ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1823 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1838 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1844 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1866 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
1872 cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
[all …]
H A Dgicv3_internal.h138 #define ICC_CTLR_EL1_EOIMODE (1U << 1) macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/
H A Darm_gicv3_cpuif.c568 value |= ICC_CTLR_EL1_EOIMODE; in icv_ctlr_read()
589 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); in icv_ctlr_write()
1070 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1072 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1820 mask = ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1822 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1837 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1843 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1865 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
1871 cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
[all …]
H A Dgicv3_internal.h138 #define ICC_CTLR_EL1_EOIMODE (1U << 1) macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/
H A Darm_gicv3_cpuif.c568 value |= ICC_CTLR_EL1_EOIMODE; in icv_ctlr_read()
589 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); in icv_ctlr_write()
1070 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1072 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1820 mask = ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1822 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1837 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1843 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1865 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
1871 cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
[all …]
H A Dgicv3_internal.h138 #define ICC_CTLR_EL1_EOIMODE (1U << 1) macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/
H A Darm_gicv3_cpuif.c571 value |= ICC_CTLR_EL1_EOIMODE; in icv_ctlr_read()
592 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); in icv_ctlr_write()
1075 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1077 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1844 mask = ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1846 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el1_write()
1861 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1867 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
1889 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
1895 cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
[all …]
H A Dgicv3_internal.h146 #define ICC_CTLR_EL1_EOIMODE (1U << 1) macro