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Searched refs:ICH_VMCR_EL2_VBPR0_SHIFT (Results 1 – 18 of 18) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/hw/intc/
H A Dgicv3_internal.h176 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 macro
178 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
H A Darm_gicv3_cpuif.c102 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
124 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
2053 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); in icc_reset()
/dports/emulators/qemu60/qemu-6.0.0/hw/intc/
H A Dgicv3_internal.h176 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 macro
178 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
H A Darm_gicv3_cpuif.c102 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
124 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
2057 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); in icc_reset()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/
H A Dgicv3_internal.h176 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 macro
178 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
H A Darm_gicv3_cpuif.c101 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
123 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
2051 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); in icc_reset()
/dports/emulators/qemu5/qemu-5.2.0/hw/intc/
H A Dgicv3_internal.h176 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 macro
178 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
H A Darm_gicv3_cpuif.c102 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
124 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
2057 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); in icc_reset()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/
H A Dgicv3_internal.h176 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 macro
178 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
H A Darm_gicv3_cpuif.c102 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
124 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
2053 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); in icc_reset()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/
H A Dgicv3_internal.h176 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 macro
178 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
H A Darm_gicv3_cpuif.c102 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
124 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
2056 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); in icc_reset()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/
H A Dgicv3_internal.h176 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 macro
178 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
H A Darm_gicv3_cpuif.c102 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
124 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
2056 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); in icc_reset()
/dports/emulators/qemu/qemu-6.2.0/hw/intc/
H A Dgicv3_internal.h184 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 macro
186 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
H A Darm_gicv3_cpuif.c103 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
125 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
2080 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); in icc_reset()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/
H A Dgicv3_internal.h184 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 macro
186 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
H A Darm_gicv3_cpuif.c103 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
125 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
2080 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); in icc_reset()