/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | m10300-opc.c | 136 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 140 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1009 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | m10300-opc.c | 138 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 142 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1011 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | m10300-opc.c | 138 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 142 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1011 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | m10300-opc.c | 135 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 139 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1008 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | m10300-opc.c | 138 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 142 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1011 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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/dports/devel/avr-gdb/gdb-7.3.1/opcodes/ |
H A D | m10300-opc.c | 139 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 143 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1012 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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/dports/devel/gdb761/gdb-7.6.1/opcodes/ |
H A D | m10300-opc.c | 139 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 143 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1012 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | m10300-opc.c | 138 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 142 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1011 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | m10300-opc.c | 138 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 142 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1011 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | m10300-opc.c | 135 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 139 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1008 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | m10300-opc.c | 136 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 140 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1009 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | m10300-opc.c | 138 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) macro 142 #define SP (IMM32_HIGH24_LOWSHIFT16+1) 1011 { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
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