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Searched refs:INEXACT (Results 1 – 25 of 219) sorted by relevance

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/dports/emulators/qemu-utils/qemu-4.2.1/tests/tcg/arm/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
H A Dfcvt.ref33 14 HALF: 0x400 (0x10 => INEXACT )
41 18 HALF: 0x4170 (0x10 => INEXACT )
43 19 HALF: 0x4248 (0x10 => INEXACT )
45 20 HALF: 0x7bff (0x10 => INEXACT )
49 22 HALF: 0x7bff (0x10 => INEXACT )
151 10 HALF: 0000 (0x10 => INEXACT )
153 11 HALF: 0000 (0x10 => INEXACT )
157 13 HALF: 0000 (0x10 => INEXACT )
159 14 HALF: 0000 (0x10 => INEXACT )
161 15 HALF: 0000 (0x10 => INEXACT )
[all …]
/dports/emulators/qemu5/qemu-5.2.0/tests/tcg/arm/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
H A Dfcvt.ref33 14 HALF: 0x400 (0x10 => INEXACT )
41 18 HALF: 0x4170 (0x10 => INEXACT )
43 19 HALF: 0x4248 (0x10 => INEXACT )
45 20 HALF: 0x7bff (0x10 => INEXACT )
49 22 HALF: 0x7bff (0x10 => INEXACT )
151 10 HALF: 0000 (0x10 => INEXACT )
153 11 HALF: 0000 (0x10 => INEXACT )
157 13 HALF: 0000 (0x10 => INEXACT )
159 14 HALF: 0000 (0x10 => INEXACT )
161 15 HALF: 0000 (0x10 => INEXACT )
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tests/tcg/arm/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
H A Dfcvt.ref33 14 HALF: 0x400 (0x10 => INEXACT )
41 18 HALF: 0x4170 (0x10 => INEXACT )
43 19 HALF: 0x4248 (0x10 => INEXACT )
45 20 HALF: 0x7bff (0x10 => INEXACT )
49 22 HALF: 0x7bff (0x10 => INEXACT )
151 10 HALF: 0000 (0x10 => INEXACT )
153 11 HALF: 0000 (0x10 => INEXACT )
157 13 HALF: 0000 (0x10 => INEXACT )
159 14 HALF: 0000 (0x10 => INEXACT )
161 15 HALF: 0000 (0x10 => INEXACT )
[all …]
/dports/emulators/qemu42/qemu-4.2.1/tests/tcg/arm/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
H A Dfcvt.ref33 14 HALF: 0x400 (0x10 => INEXACT )
41 18 HALF: 0x4170 (0x10 => INEXACT )
43 19 HALF: 0x4248 (0x10 => INEXACT )
45 20 HALF: 0x7bff (0x10 => INEXACT )
49 22 HALF: 0x7bff (0x10 => INEXACT )
151 10 HALF: 0000 (0x10 => INEXACT )
153 11 HALF: 0000 (0x10 => INEXACT )
157 13 HALF: 0000 (0x10 => INEXACT )
159 14 HALF: 0000 (0x10 => INEXACT )
161 15 HALF: 0000 (0x10 => INEXACT )
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tests/tcg/arm/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/emulators/qemu/qemu-6.2.0/tests/tcg/arm/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/tests/tcg/arm/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/emulators/qemu60/qemu-6.0.0/tests/tcg/arm/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tests/tcg/hexagon/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
64 to int32: 0 (INEXACT )
65 to int64: 0 (INEXACT )
66 to uint32: 0 (INEXACT )
67 to uint64: 0 (INEXACT )
[all …]
/dports/emulators/qemu/qemu-6.2.0/tests/tcg/hexagon/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
64 to int32: 0 (INEXACT )
65 to int64: 0 (INEXACT )
66 to uint32: 0 (INEXACT )
67 to uint64: 0 (INEXACT )
[all …]
/dports/emulators/qemu60/qemu-6.0.0/tests/tcg/hexagon/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
64 to int32: 0 (INEXACT )
65 to int64: 0 (INEXACT )
66 to uint32: 0 (INEXACT )
67 to uint64: 0 (INEXACT )
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/tests/tcg/aarch64/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/emulators/qemu5/qemu-5.2.0/tests/tcg/aarch64/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tests/tcg/aarch64/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/emulators/qemu42/qemu-4.2.1/tests/tcg/aarch64/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tests/tcg/aarch64/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/emulators/qemu/qemu-6.2.0/tests/tcg/aarch64/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/tests/tcg/aarch64/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/emulators/qemu60/qemu-6.0.0/tests/tcg/aarch64/
H A Dfloat_convs.ref40 to int32: 0 (INEXACT )
41 to int64: 0 (INEXACT )
42 to uint32: 0 (INEXACT )
43 to uint64: 0 (INEXACT )
46 to int32: 0 (INEXACT )
47 to int64: 0 (INEXACT )
48 to uint32: 0 (INEXACT )
49 to uint64: 0 (INEXACT )
52 to int32: 0 (INEXACT )
53 to int64: 0 (INEXACT )
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/cheri/
H A Dcheri-capcmp.ll7 ; CHECK-INEXACT-LABEL: eq:
8 ; CHECK-INEXACT: # %bb.0:
9 ; CHECK-INEXACT-NEXT: jr $ra
22 ; CHECK-INEXACT-LABEL: ne:
37 ; CHECK-INEXACT-LABEL: lt:
51 ; CHECK-INEXACT-LABEL: ult:
66 ; CHECK-INEXACT-LABEL: le:
81 ; CHECK-INEXACT-LABEL: ule:
96 ; CHECK-INEXACT-LABEL: gt:
111 ; CHECK-INEXACT-LABEL: ugt:
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tests/tcg/arm/
H A Dfcvt.ref33 14 HALF: 0x400 (0x10 => INEXACT )
41 18 HALF: 0x4170 (0x10 => INEXACT )
43 19 HALF: 0x4248 (0x10 => INEXACT )
45 20 HALF: 0x7bff (0x10 => INEXACT )
49 22 HALF: 0x7bff (0x10 => INEXACT )
151 10 HALF: 0000 (0x10 => INEXACT )
153 11 HALF: 0000 (0x10 => INEXACT )
157 13 HALF: 0000 (0x10 => INEXACT )
159 14 HALF: 0000 (0x10 => INEXACT )
161 15 HALF: 0000 (0x10 => INEXACT )
[all …]

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