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/dports/graphics/geomview/geomview-1.9.5/data/geom/textured/
H A Dlunar-t.oogl11 geom { INST
19 geom { INST
27 geom { INST
38 { INST
54 geom { INST
62 geom { INST
78 { INST
94 geom { INST
144 = INST
225 { INST
[all …]
/dports/audio/sayonara/sayonara-player-5bbf1399332d5d59362ad03bf625f9132be72206/src/Utils/Settings/
H A DSettingKey.h242 INST(QString, LFM_Username) /* username*/
252 INST(bool, Lib_Show) /* show library */
253 INST(QString, Lib_Path) // deprecated
254 INST(QByteArray, Lib_ColStateAlbums)
255 INST(QByteArray, Lib_ColStateArtists)
256 INST(QByteArray, Lib_ColStateTracks)
317 INST(QStringList,
349 INST(int, AudioConvert_QualityOgg) /* 1 - 10 */
352 INST(int, Engine_Vol) /* Volume */
361 INST(int, Engine_Pitch) /* hertz of a */
[all …]
/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A64/decoder/
H A Da64.inc2 INST(ADR, "ADR", "0ii10000iiiiiiiiiiiiiiii…
3 INST(ADRP, "ADRP", "1ii10000iiiiiiiiiiiiiiii…
10 INST(ADD_imm, "ADD (immediate)", "z0010001ssiiiiiiiiiiiinn…
11 INST(ADDS_imm, "ADDS (immediate)", "z0110001ssiiiiiiiiiiiinn…
12 INST(SUB_imm, "SUB (immediate)", "z1010001ssiiiiiiiiiiiinn…
13 INST(SUBS_imm, "SUBS (immediate)", "z1110001ssiiiiiiiiiiiinn…
16 INST(AND_imm, "AND (immediate)", "z00100100Nrrrrrrssssssnn…
17 INST(ORR_imm, "ORR (immediate)", "z01100100Nrrrrrrssssssnn…
18 INST(EOR_imm, "EOR (immediate)", "z10100100Nrrrrrrssssssnn…
19 INST(ANDS_imm, "ANDS (immediate)", "z11100100Nrrrrrrssssssnn…
[all …]
/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/A64/decoder/
H A Da64.inc2 INST(ADR, "ADR", "0ii10000iiiiiiiiiiiiiiii…
3 INST(ADRP, "ADRP", "1ii10000iiiiiiiiiiiiiiii…
10 INST(ADD_imm, "ADD (immediate)", "z0010001ssiiiiiiiiiiiinn…
11 INST(ADDS_imm, "ADDS (immediate)", "z0110001ssiiiiiiiiiiiinn…
12 INST(SUB_imm, "SUB (immediate)", "z1010001ssiiiiiiiiiiiinn…
13 INST(SUBS_imm, "SUBS (immediate)", "z1110001ssiiiiiiiiiiiinn…
16 INST(AND_imm, "AND (immediate)", "z00100100Nrrrrrrssssssnn…
17 INST(ORR_imm, "ORR (immediate)", "z01100100Nrrrrrrssssssnn…
18 INST(EOR_imm, "EOR (immediate)", "z10100100Nrrrrrrssssssnn…
19 INST(ANDS_imm, "ANDS (immediate)", "z11100100Nrrrrrrssssssnn…
[all …]
/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/A64/decoder/
H A Da64.inc2 INST(ADR, "ADR", "0ii10000iiiiiiiiiiiiiiii…
3 INST(ADRP, "ADRP", "1ii10000iiiiiiiiiiiiiiii…
10 INST(ADD_imm, "ADD (immediate)", "z0010001ssiiiiiiiiiiiinn…
11 INST(ADDS_imm, "ADDS (immediate)", "z0110001ssiiiiiiiiiiiinn…
12 INST(SUB_imm, "SUB (immediate)", "z1010001ssiiiiiiiiiiiinn…
13 INST(SUBS_imm, "SUBS (immediate)", "z1110001ssiiiiiiiiiiiinn…
16 INST(AND_imm, "AND (immediate)", "z00100100Nrrrrrrssssssnn…
17 INST(ORR_imm, "ORR (immediate)", "z01100100Nrrrrrrssssssnn…
18 INST(EOR_imm, "EOR (immediate)", "z10100100Nrrrrrrssssssnn…
19 INST(ANDS_imm, "ANDS (immediate)", "z11100100Nrrrrrrssssssnn…
[all …]
/dports/biology/avida/avida-2.12.4-src/avida-core/tests/avatars/config/
H A Dinstset.cfg4 INST nop-A # a
5 INST nop-B # b
6 INST nop-C # c
14 INST if-n-equ
25 INST label
34 INST pop-all
35 INST push-all
50 INST id-thread
68 INST if-gtr-x
87 INST rotate-x
[all …]
/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/A32/decoder/
H A Darm_a64.inc2 //INST(arm_DMB, "DMB", "1111010101111111111100000101oooo") // v7
3 //INST(arm_DSB, "DSB", "1111010101111111111100000100oooo") // v7
4 //INST(arm_ISB, "ISB", "1111010101111111111100000110oooo") // v7
7 INST(arm_BLX_imm, "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv") // v5
8 INST(arm_BLX_reg, "BLX (reg)", "cccc000100101111111111110011mmmm") // v5
9 INST(arm_B, "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv") // all
10 INST(arm_BL, "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv") // all
11 INST(arm_BX, "BX", "cccc000100101111111111110001mmmm") // v4T
12 INST(arm_BXJ, "BXJ", "cccc000100101111111111110010mmmm") // v5J
104 INST(arm_NOP, "Reserved Hint", "----0011001000001111------------")
[all …]
H A Darm.inc2 INST(arm_DMB, "DMB", "1111010101111111111100000101oooo") // v7
3 INST(arm_DSB, "DSB", "1111010101111111111100000100oooo") // v7
4 INST(arm_ISB, "ISB", "1111010101111111111100000110oooo") // v7
7 INST(arm_BLX_imm, "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv") // v5
8 INST(arm_BLX_reg, "BLX (reg)", "cccc000100101111111111110011mmmm") // v5
9 INST(arm_B, "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv") // all
10 INST(arm_BL, "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv") // all
11 INST(arm_BX, "BX", "cccc000100101111111111110001mmmm") // v4T
12 INST(arm_BXJ, "BXJ", "cccc000100101111111111110010mmmm") // v5J
15 INST(arm_CRC32, "CRC32", "cccc00010zz0nnnndddd00000100mmmm") // v8
[all …]
H A Dthumb16.h29 INST(&V::thumb16_LSL_imm, "LSL (imm)", "00000vvvvvmmmddd"), in DecodeThumb16()
30 INST(&V::thumb16_LSR_imm, "LSR (imm)", "00001vvvvvmmmddd"), in DecodeThumb16()
31 INST(&V::thumb16_ASR_imm, "ASR (imm)", "00010vvvvvmmmddd"), in DecodeThumb16()
32 INST(&V::thumb16_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd"), in DecodeThumb16()
33 INST(&V::thumb16_SUB_reg, "SUB (reg)", "0001101mmmnnnddd"), in DecodeThumb16()
34 INST(&V::thumb16_ADD_imm_t1, "ADD (imm, T1)", "0001110vvvnnnddd"), in DecodeThumb16()
35 INST(&V::thumb16_SUB_imm_t1, "SUB (imm, T1)", "0001111vvvnnnddd"), in DecodeThumb16()
36 INST(&V::thumb16_MOV_imm, "MOV (imm)", "00100dddvvvvvvvv"), in DecodeThumb16()
37 INST(&V::thumb16_CMP_imm, "CMP (imm)", "00101nnnvvvvvvvv"), in DecodeThumb16()
38 INST(&V::thumb16_ADD_imm_t2, "ADD (imm, T2)", "00110dddvvvvvvvv"), in DecodeThumb16()
[all …]
H A Dasimd.inc2 INST(asimd_VHADD, "VHADD", "1111001U0Dzznnnndddd0000NQM0mmmm") // ASIMD
3 INST(asimd_VQADD, "VQADD", "1111001U0Dzznnnndddd0000NQM1mmmm") // ASIMD
4 INST(asimd_VRHADD, "VRHADD", "1111001U0Dzznnnndddd0001NQM0mmmm") // ASIMD
5 INST(asimd_VAND_reg, "VAND (register)", "111100100D00nnnndddd0001NQM1mmmm") // ASIMD
6 INST(asimd_VBIC_reg, "VBIC (register)", "111100100D01nnnndddd0001NQM1mmmm") // ASIMD
7 INST(asimd_VORR_reg, "VORR (register)", "111100100D10nnnndddd0001NQM1mmmm") // ASIMD
8 INST(asimd_VORN_reg, "VORN (register)", "111100100D11nnnndddd0001NQM1mmmm") // ASIMD
9 INST(asimd_VEOR_reg, "VEOR (register)", "111100110D00nnnndddd0001NQM1mmmm") // ASIMD
10 INST(asimd_VBSL, "VBSL", "111100110D01nnnndddd0001NQM1mmmm") // ASIMD
11 INST(asimd_VBIT, "VBIT", "111100110D10nnnndddd0001NQM1mmmm") // ASIMD
[all …]
/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/A32/decoder/
H A Darm_a64.inc2 //INST(arm_DMB, "DMB", "1111010101111111111100000101oooo") // v7
3 //INST(arm_DSB, "DSB", "1111010101111111111100000100oooo") // v7
4 //INST(arm_ISB, "ISB", "1111010101111111111100000110oooo") // v7
7 INST(arm_BLX_imm, "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv") // v5
8 INST(arm_BLX_reg, "BLX (reg)", "cccc000100101111111111110011mmmm") // v5
9 INST(arm_B, "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv") // all
10 INST(arm_BL, "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv") // all
11 INST(arm_BX, "BX", "cccc000100101111111111110001mmmm") // v4T
12 INST(arm_BXJ, "BXJ", "cccc000100101111111111110010mmmm") // v5J
104 INST(arm_NOP, "Reserved Hint", "----0011001000001111------------")
[all …]
H A Darm.inc2 INST(arm_DMB, "DMB", "1111010101111111111100000101oooo") // v7
3 INST(arm_DSB, "DSB", "1111010101111111111100000100oooo") // v7
4 INST(arm_ISB, "ISB", "1111010101111111111100000110oooo") // v7
7 INST(arm_BLX_imm, "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv") // v5
8 INST(arm_BLX_reg, "BLX (reg)", "cccc000100101111111111110011mmmm") // v5
9 INST(arm_B, "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv") // all
10 INST(arm_BL, "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv") // all
11 INST(arm_BX, "BX", "cccc000100101111111111110001mmmm") // v4T
12 INST(arm_BXJ, "BXJ", "cccc000100101111111111110010mmmm") // v5J
15 INST(arm_CRC32, "CRC32", "cccc00010zz0nnnndddd00000100mmmm") // v8
[all …]
H A Dthumb16.h29 INST(&V::thumb16_LSL_imm, "LSL (imm)", "00000vvvvvmmmddd"), in DecodeThumb16()
30 INST(&V::thumb16_LSR_imm, "LSR (imm)", "00001vvvvvmmmddd"), in DecodeThumb16()
31 INST(&V::thumb16_ASR_imm, "ASR (imm)", "00010vvvvvmmmddd"), in DecodeThumb16()
32 INST(&V::thumb16_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd"), in DecodeThumb16()
33 INST(&V::thumb16_SUB_reg, "SUB (reg)", "0001101mmmnnnddd"), in DecodeThumb16()
34 INST(&V::thumb16_ADD_imm_t1, "ADD (imm, T1)", "0001110vvvnnnddd"), in DecodeThumb16()
35 INST(&V::thumb16_SUB_imm_t1, "SUB (imm, T1)", "0001111vvvnnnddd"), in DecodeThumb16()
36 INST(&V::thumb16_MOV_imm, "MOV (imm)", "00100dddvvvvvvvv"), in DecodeThumb16()
37 INST(&V::thumb16_CMP_imm, "CMP (imm)", "00101nnnvvvvvvvv"), in DecodeThumb16()
38 INST(&V::thumb16_ADD_imm_t2, "ADD (imm, T2)", "00110dddvvvvvvvv"), in DecodeThumb16()
[all …]
H A Dasimd.inc2 INST(asimd_VHADD, "VHADD", "1111001U0Dzznnnndddd0000NQM0mmmm") // ASIMD
3 INST(asimd_VQADD, "VQADD", "1111001U0Dzznnnndddd0000NQM1mmmm") // ASIMD
4 INST(asimd_VRHADD, "VRHADD", "1111001U0Dzznnnndddd0001NQM0mmmm") // ASIMD
5 INST(asimd_VAND_reg, "VAND (register)", "111100100D00nnnndddd0001NQM1mmmm") // ASIMD
6 INST(asimd_VBIC_reg, "VBIC (register)", "111100100D01nnnndddd0001NQM1mmmm") // ASIMD
7 INST(asimd_VORR_reg, "VORR (register)", "111100100D10nnnndddd0001NQM1mmmm") // ASIMD
8 INST(asimd_VORN_reg, "VORN (register)", "111100100D11nnnndddd0001NQM1mmmm") // ASIMD
9 INST(asimd_VEOR_reg, "VEOR (register)", "111100110D00nnnndddd0001NQM1mmmm") // ASIMD
10 INST(asimd_VBSL, "VBSL", "111100110D01nnnndddd0001NQM1mmmm") // ASIMD
11 INST(asimd_VBIT, "VBIT", "111100110D10nnnndddd0001NQM1mmmm") // ASIMD
[all …]
/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A32/decoder/
H A Darm.inc2 INST(arm_DMB, "DMB", "1111010101111111111100000101oooo") // v7
3 INST(arm_DSB, "DSB", "1111010101111111111100000100oooo") // v7
4 INST(arm_ISB, "ISB", "1111010101111111111100000110oooo") // v7
7 INST(arm_BLX_imm, "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv") // v5
8 INST(arm_BLX_reg, "BLX (reg)", "cccc000100101111111111110011mmmm") // v5
9 INST(arm_B, "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv") // all
10 INST(arm_BL, "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv") // all
11 INST(arm_BX, "BX", "cccc000100101111111111110001mmmm") // v4T
12 INST(arm_BXJ, "BXJ", "cccc000100101111111111110010mmmm") // v5J
15 INST(arm_CRC32, "CRC32", "cccc00010zz0nnnndddd00000100mmmm") // v8
[all …]
H A Dthumb16.h29 INST(&V::thumb16_LSL_imm, "LSL (imm)", "00000vvvvvmmmddd"), in DecodeThumb16()
30 INST(&V::thumb16_LSR_imm, "LSR (imm)", "00001vvvvvmmmddd"), in DecodeThumb16()
31 INST(&V::thumb16_ASR_imm, "ASR (imm)", "00010vvvvvmmmddd"), in DecodeThumb16()
32 INST(&V::thumb16_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd"), in DecodeThumb16()
33 INST(&V::thumb16_SUB_reg, "SUB (reg)", "0001101mmmnnnddd"), in DecodeThumb16()
34 INST(&V::thumb16_ADD_imm_t1, "ADD (imm, T1)", "0001110vvvnnnddd"), in DecodeThumb16()
35 INST(&V::thumb16_SUB_imm_t1, "SUB (imm, T1)", "0001111vvvnnnddd"), in DecodeThumb16()
36 INST(&V::thumb16_MOV_imm, "MOV (imm)", "00100dddvvvvvvvv"), in DecodeThumb16()
37 INST(&V::thumb16_CMP_imm, "CMP (imm)", "00101nnnvvvvvvvv"), in DecodeThumb16()
38 INST(&V::thumb16_ADD_imm_t2, "ADD (imm, T2)", "00110dddvvvvvvvv"), in DecodeThumb16()
[all …]
H A Dasimd.inc2 INST(asimd_VHADD, "VHADD", "1111001U0Dzznnnndddd0000NQM0mmmm") // ASIMD
3 INST(asimd_VQADD, "VQADD", "1111001U0Dzznnnndddd0000NQM1mmmm") // ASIMD
4 INST(asimd_VRHADD, "VRHADD", "1111001U0Dzznnnndddd0001NQM0mmmm") // ASIMD
5 INST(asimd_VAND_reg, "VAND (register)", "111100100D00nnnndddd0001NQM1mmmm") // ASIMD
6 INST(asimd_VBIC_reg, "VBIC (register)", "111100100D01nnnndddd0001NQM1mmmm") // ASIMD
7 INST(asimd_VORR_reg, "VORR (register)", "111100100D10nnnndddd0001NQM1mmmm") // ASIMD
123 INST(arm_UDF, "UNALLOCATED (VRINTN)", "111100111-11--10----01000--0----")
124 INST(arm_UDF, "UNALLOCATED (VRINTX)", "111100111-11--10----01001--0----")
125 INST(arm_UDF, "UNALLOCATED (VRINTA)", "111100111-11--10----01010--0----")
126 INST(arm_UDF, "UNALLOCATED (VRINTZ)", "111100111-11--10----01011--0----")
[all …]
/dports/biology/avida/avida-2.12.4-src/avida-core/tests/gradient_inflow_common/config/
H A Dinstset.cfg4 INST nop-A # a
5 INST nop-B # b
6 INST nop-C # c
9 INST if-n-equ # d
10 INST if-less # e
11 INST if-label # f
41 INST repro
45 INST nop-X
50 INST rotate-home
55 INST move
[all …]
/dports/biology/avida/avida-2.12.4-src/avida-core/tests/gradient_halo_generate/config/
H A Dinstset.cfg4 INST nop-A # a
5 INST nop-B # b
6 INST nop-C # c
9 INST if-n-equ # d
10 INST if-less # e
11 INST if-label # f
41 INST repro
45 INST nop-X
50 INST rotate-home
55 INST move
[all …]
/dports/biology/avida/avida-2.12.4-src/avida-core/tests/gradient_inflow_nocommon/config/
H A Dinstset.cfg4 INST nop-A # a
5 INST nop-B # b
6 INST nop-C # c
9 INST if-n-equ # d
10 INST if-less # e
11 INST if-label # f
41 INST repro
45 INST nop-X
50 INST rotate-home
55 INST move
[all …]
/dports/biology/avida/avida-2.12.4-src/avida-core/tests/gradient_regular_generate/config/
H A Dinstset.cfg4 INST nop-A # a
5 INST nop-B # b
6 INST nop-C # c
9 INST if-n-equ # d
10 INST if-less # e
11 INST if-label # f
41 INST repro
45 INST nop-X
50 INST rotate-home
55 INST move
[all …]
/dports/biology/avida/avida-2.12.4-src/avida-core/tests/gradient_regular_move/config/
H A Dinstset.cfg4 INST nop-A # a
5 INST nop-B # b
6 INST nop-C # c
9 INST if-n-equ # d
10 INST if-less # e
11 INST if-label # f
41 INST repro
45 INST nop-X
50 INST rotate-home
55 INST move
[all …]
/dports/emulators/citra/citra-ac98458e0/externals/teakra/src/
H A Ddecoder.h98 INST(nop, 0x0000),
101 INST(trap, 0x0020),
238 INST(bankr, 0x8CDF),
253 INST(break_, 0xD3C0),
262 INST(cntx_s, 0xD380),
267 INST(retd, 0xD780),
270 INST(retid, 0xD7C0),
336 INST(dint, 0x43C0),
337 INST(eint, 0x4380),
527 INST(clrp, 0x5DFF),
[all …]
/dports/emulators/citra-qt5/citra-ac98458e0/externals/teakra/src/
H A Ddecoder.h98 INST(nop, 0x0000),
101 INST(trap, 0x0020),
238 INST(bankr, 0x8CDF),
253 INST(break_, 0xD3C0),
262 INST(cntx_s, 0xD380),
267 INST(retd, 0xD780),
270 INST(retid, 0xD7C0),
336 INST(dint, 0x43C0),
337 INST(eint, 0x4380),
527 INST(clrp, 0x5DFF),
[all …]
/dports/emulators/spim/spim-8.0/CPU/
H A Dinst.h95 #define OPCODE(INST) (INST)->opcode argument
99 #define RS(INST) (INST)->r_t.r_i.rs argument
109 #define FS(INST) RD(INST) argument
112 #define FT(INST) RT(INST) argument
115 #define FD(INST) SHAMT(INST) argument
126 #define BASE(INST) RS(INST) argument
129 #define IOFFSET(INST) IMM(INST) argument
134 #define COND(INST) RS(INST) argument
137 #define CC(INST) (RT(INST) >> 2) argument
139 #define TF(INST) (RT(INST) & 0x1) argument
[all …]

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