1 /* Copyright (c) 2002, Colin O'Flynn 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* avr/io86r401.h - definitions for AT86RF401 */ 32 33 /* $Id: io86r401.h 2436 2014-08-11 10:37:37Z joerg_wunsch $ */ 34 35 #ifndef _AVR_IO86RF401_H_ 36 #define _AVR_IO86RF401_H_ 1 37 38 /* This file should only be included from <avr/io.h>, never directly. */ 39 40 #ifndef _AVR_IO_H_ 41 # error "Include <avr/io.h> instead of this file." 42 #endif 43 44 #ifndef _AVR_IOXXX_H_ 45 # define _AVR_IOXXX_H_ "io86r401.h" 46 #else 47 # error "Attempt to include more than one <avr/ioXXX.h> file." 48 #endif 49 50 #include <avr/sfr_defs.h> 51 52 /* Status REGister */ 53 #define SREG _SFR_IO8(0x3F) 54 55 /* Stack Pointer */ 56 #define SP _SFR_IO16(0x3D) 57 #define SPH _SFR_IO8(0x3E) 58 #define SPL _SFR_IO8(0x3D) 59 60 /*Battery low configeration register */ 61 #define BL_CONFIG _SFR_IO8(0x35) 62 63 /*Button detect register*/ 64 #define B_DET _SFR_IO8(0x34) 65 66 /*AVR Configeration register*/ 67 #define AVR_CONFIG _SFR_IO8(0x33) 68 69 /* I/O registers */ 70 71 /*Data in register */ 72 #define IO_DATIN _SFR_IO8(0x32) 73 74 /*Data out register */ 75 #define IO_DATOUT _SFR_IO8(0x31) 76 77 /*IO Enable register */ 78 #define IO_ENAB _SFR_IO8(0x30) 79 80 /* Watchdog Timer Control Register */ 81 #define WDTCR _SFR_IO8(0x22) 82 83 /* Bit Timer Control Register */ 84 #define BTCR _SFR_IO8(0x21) 85 86 #define BTCNT _SFR_IO8(0x20) 87 88 /* 89 NOTE: EEPROM name's changed to have D in front on them, per datasheet, but 90 you may want to remove the leading D. 91 */ 92 /* EEPROM Control Register */ 93 94 /* EEPROM Address Register */ 95 #define DEEAR _SFR_IO8(0x1E) 96 #define DEEARL _SFR_IO8(0x1E) 97 98 /* EEPROM Data Register */ 99 #define DEEDR _SFR_IO8(0x1D) 100 /* EEPROM Control Register */ 101 #define DEECR _SFR_IO8(0x1C) 102 103 /* Lock Detector Configuration Register 2 */ 104 #define LOCKDET2 _SFR_IO8(0x17) 105 106 /* VCO Tuning Register*/ 107 #define VCOTUNE _SFR_IO8(0x16) 108 109 /* Power Attenuation Control Register */ 110 #define PWR_ATTEN _SFR_IO8(0x14) 111 112 /* Transmitter Control Register */ 113 #define TX_CNTL _SFR_IO8(0x12) 114 115 /* Lock Detector Configuration Register 1 */ 116 #define LOCKDET1 _SFR_IO8(0x10) 117 118 119 /* Interrupt vectors */ 120 121 /* Transmission Done, Bit Timer Flag 2 Interrupt */ 122 #define TXDONE_vect_num 1 123 #define TXDONE_vect _VECTOR(1) 124 #define SIG_TXDONE _VECTOR(1) 125 126 /* Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt */ 127 #define TXEMPTY_vect_num 2 128 #define TXEMPTY_vect _VECTOR(2) 129 #define SIG_TXBE _VECTOR(2) 130 131 #define _VECTORS_SIZE 12 132 133 /* 134 * The Register Bit names are represented by their bit number (0-7). 135 */ 136 137 /* Lock Detector Configuration Register 1 - LOCKDET1 */ 138 #define UPOK 4 139 #define ENKO 3 140 #define BOD 2 141 #define CS1 1 142 #define CS0 0 143 144 /* Transmit Control Register - TX_CNTL */ 145 #define TXE 5 146 #define TXK 4 147 #define LOC 2 148 149 /* Power Attenuation Control Register - PWR_ATTEN */ 150 #define PCC2 5 151 #define PCC1 4 152 #define PCC0 3 153 #define PCF2 2 154 #define PCF1 1 155 #define PCF0 0 156 157 /* VCO Tuning Register 6 - VCOTUNE --NOTE: [] removed from names*/ 158 #define VCOVDET1 7 159 #define VCOVDET0 6 160 #define VCOTUNE4 4 161 #define VCOTUNE3 3 162 #define VCOTUNE2 2 163 #define VCOTUNE1 1 164 #define VCOTUNE0 0 165 166 /* Lock Detector Configuration Register 2 - LOCKDET2 --NOTE: [] removed from names*/ 167 #define EUD 7 168 #define LAT 6 169 #define ULC2 5 170 #define ULC1 4 171 #define ULC0 3 172 #define LC2 2 173 #define LC1 1 174 #define LC0 0 175 176 /* Data EEPROM Control Register - DEECR */ 177 #define BSY 3 178 #define EEU 2 179 #define EEL 1 180 #define EER 0 181 182 /* Data EEPROM Data Register - DEEDR */ 183 #define ED7 7 184 #define ED6 6 185 #define ED5 5 186 #define ED4 4 187 #define ED3 3 188 #define ED2 2 189 #define ED1 1 190 #define ED0 0 191 192 /* Data EEPROM Address Register - DEEAR */ 193 #define PA6 6 194 #define PA5 5 195 #define PA4 4 196 #define PA3 3 197 #define BA2 2 /* B is not a typo! */ 198 #define BA1 1 199 #define BA0 0 200 201 /* Bit Timer Count Register - BTCNT */ 202 #define C7 7 203 #define C6 6 204 #define C5 5 205 #define C4 4 206 #define C3 3 207 #define C2 2 208 #define C1 1 209 #define C0 0 210 211 /* Bit Timer Control Register - BTCR */ 212 #define C9 7 213 #define C8 6 214 #define M1 5 215 #define M0 4 216 #define IE 3 217 #define F2 2 218 #define DATA 1 219 #define F0 0 220 221 /* Watchdog Timer Control Register - WDTCR */ 222 #define WDTOE 4 223 #define WDE 3 224 #define WDP2 2 225 #define WDP1 1 226 #define WDP0 0 227 228 /* I/O Enable Register - IO_ENAB */ 229 #define BOHYST 6 230 #define IOE5 5 231 #define IOE4 4 232 #define IOE3 3 233 #define IOE2 2 234 #define IOE1 1 235 #define IOE0 0 236 237 /* Note: No PORTB or whatever, this is the equivalent. */ 238 /* I/O Data Out Register - IO_DATOUT */ 239 #define IOO5 5 240 #define IOO4 4 241 #define IOO3 3 242 #define IOO2 2 243 #define IOO1 1 244 #define IOO0 0 245 246 /* Note: No PINB or whatever, this is the equivalent. */ 247 /* I/O Data In Register - IO_DATIN */ 248 #define IOI5 5 249 #define IOI4 4 250 #define IOI3 3 251 #define IOI2 2 252 #define IOI1 1 253 #define IOI0 0 254 255 /* AVR Configuration Register - AVR_CONFIG */ 256 #define ACS1 6 257 #define ACS0 5 258 #define TM 4 259 #define BD 3 260 #define BLI 2 261 #define SLEEP 1 262 #define BBM 0 263 264 /* Button Detect Register - B_DET */ 265 #define BD5 5 266 #define BD4 4 267 #define BD3 3 268 #define BD2 2 269 #define BD1 1 270 #define BD0 0 271 272 /* Battery Low Configuration Register - BL_CONFIG */ 273 #define BL 7 274 #define BLV 6 275 #define BL5 5 276 #define BL4 4 277 #define BL3 3 278 #define BL2 2 279 #define BL1 1 280 #define BL0 0 281 282 /* Pointer definition */ 283 #define XL r26 284 #define XH r27 285 #define YL r28 286 #define YH r29 287 #define ZL r30 288 #define ZH r31 289 290 /* Constants */ 291 #define RAMSTART 0x60 292 #define RAMEND 0xDF 293 #define XRAMEND RAMEND 294 #define E2END 0x7F 295 #define E2PAGESIZE 0 296 #define FLASHEND 0x07FF 297 298 299 /* Fuses */ 300 #define FUSE_MEMORY_SIZE 0 301 302 303 /* Lock Bits */ 304 #define __LOCK_BITS_EXIST 305 306 307 /* Signature */ 308 #define SIGNATURE_0 0x1E 309 #define SIGNATURE_1 0x91 310 #define SIGNATURE_2 0x81 311 312 313 #endif /* _AVR_IO86RF401_H_ */ 314