| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/ |
| H A D | cpu_bits.h | 499 #define IRQ_U_TIMER 4 macro
513 #define MIP_UTIP (1 << IRQ_U_TIMER)
531 #define MIE_UTIE (1 << IRQ_U_TIMER)
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| /dports/emulators/qemu5/qemu-5.2.0/target/riscv/ |
| H A D | cpu_bits.h | 560 #define IRQ_U_TIMER 4 macro
574 #define MIP_UTIP (1 << IRQ_U_TIMER)
592 #define MIE_UTIE (1 << IRQ_U_TIMER)
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/riscv/ |
| H A D | cpu_bits.h | 542 #define IRQ_U_TIMER 4 macro
556 #define MIP_UTIP (1 << IRQ_U_TIMER)
574 #define MIE_UTIE (1 << IRQ_U_TIMER)
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| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/riscv/ |
| H A D | cpu_bits.h | 549 #define IRQ_U_TIMER 4 macro
563 #define MIP_UTIP (1 << IRQ_U_TIMER)
581 #define MIE_UTIE (1 << IRQ_U_TIMER)
|
| /dports/emulators/qemu/qemu-6.2.0/target/riscv/ |
| H A D | cpu_bits.h | 519 #define IRQ_U_TIMER 4 macro
533 #define MIP_UTIP (1 << IRQ_U_TIMER)
551 #define MIE_UTIE (1 << IRQ_U_TIMER)
|
| /dports/emulators/qemu60/qemu-6.0.0/target/riscv/ |
| H A D | cpu_bits.h | 560 #define IRQ_U_TIMER 4 macro
574 #define MIP_UTIP (1 << IRQ_U_TIMER)
592 #define MIE_UTIE (1 << IRQ_U_TIMER)
|
| /dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/ |
| H A D | cpu_bits.h | 508 #define IRQ_U_TIMER 4 macro
522 #define MIP_UTIP (1 << IRQ_U_TIMER)
|
| /dports/emulators/qemu42/qemu-4.2.1/target/riscv/ |
| H A D | cpu_bits.h | 508 #define IRQ_U_TIMER 4 macro
522 #define MIP_UTIP (1 << IRQ_U_TIMER)
|
| /dports/sysutils/u-boot-tools/u-boot-2020.07/arch/riscv/include/asm/ |
| H A D | csr.h | 55 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/riscv/include/asm/ |
| H A D | csr.h | 77 #define IRQ_U_TIMER 4 macro
|