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Searched refs:IS_CE_INVERTED (Results 1 – 2 of 2) sorted by relevance

/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/
H A Dcells_sim.v159 parameter [0:0] IS_CE_INVERTED = 1'b0; constant
161 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
617 parameter [0:0] IS_CE_INVERTED = 1'b0; constant
623 wire ce = CE ^ IS_CE_INVERTED;
652 parameter [0:0] IS_CE_INVERTED = 1'b0; constant
658 wire ce = CE ^ IS_CE_INVERTED;
H A Dcells_xtra.v7294 parameter [0:0] IS_CE_INVERTED = 1'b0; constant
7380 parameter [0:0] IS_CE_INVERTED = 1'b0; constant
7493 parameter [0:0] IS_CE_INVERTED = 1'b0; constant