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Searched refs:IVL_SCT_MODULE (Results 1 – 14 of 14) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vlog95/
H A Dscope.c665 if (ivl_scope_type(ivl_scope_parent(scope)) != IVL_SCT_MODULE) return; in emit_named_block_scope()
699 while (ivl_scope_type(mod_scope) != IVL_SCT_MODULE) { in find_tfb_process()
1004 case IVL_SCT_MODULE: in emit_scope()
1130 if (sc_type == IVL_SCT_MODULE) { in emit_scope()
1138 if (sc_type == IVL_SCT_MODULE) { in emit_scope()
1218 if (sc_type == IVL_SCT_MODULE) emit_specify(scope); in emit_scope()
1224 case IVL_SCT_MODULE: in emit_scope()
H A Dmisc.c770 while ((ivl_scope_type(scope) != IVL_SCT_MODULE) && in get_module_scope()
/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dscope.cc916 assert(ivl_scope_type(scope) == IVL_SCT_MODULE); in create_skeleton_entity_for()
983 case IVL_SCT_MODULE: in draw_skeleton_scope()
1005 if (ivl_scope_type(scope) == IVL_SCT_MODULE) { in draw_all_signals()
1063 if (ivl_scope_type(scope) == IVL_SCT_MODULE) { in draw_constant_drivers()
1136 if (ivl_scope_type(scope) == IVL_SCT_MODULE) { in draw_all_logic_and_lpm()
1153 if (ivl_scope_type(scope) == IVL_SCT_MODULE && _parent) { in draw_hierarchy()
H A Dprocess.cc102 assert(ivl_scope_type(scope) == IVL_SCT_MODULE); in draw_process()
H A Dstate.cc180 assert(ivl_scope_type(scope) == IVL_SCT_MODULE); in find_entity()
H A Dexpr.cc546 assert(ivl_scope_type(parentscope) == IVL_SCT_MODULE); in translate_ufunc()
/dports/cad/iverilog/verilog-11.0/tgt-blif/
H A Dblif.cc82 if (ivl_scope_type(roots[0]) != IVL_SCT_MODULE) { in target_design()
/dports/cad/iverilog/verilog-11.0/tgt-pcb/
H A Dscope.cc124 assert(ivl_scope_type(scope) == IVL_SCT_MODULE); in black_box()
/dports/cad/iverilog/verilog-11.0/tgt-sizer/
H A Dsizer.cc95 if (ivl_scope_type(roots[idx]) != IVL_SCT_MODULE) { in target_design()
/dports/cad/iverilog/verilog-11.0/
H A Dt-dll-api.cc2266 assert(net->type_ == IVL_SCT_MODULE ); in ivl_scope_mod_module_ports()
2273 assert(net->type_ == IVL_SCT_MODULE ); in ivl_scope_mod_module_port_name()
2301 if (net->type_ == IVL_SCT_MODULE || in ivl_scope_ports()
2319 assert(net->type_ == IVL_SCT_MODULE); in ivl_scope_mod_port()
H A Divl_target.h370 IVL_SCT_MODULE = 0, enumerator
H A Dt-dll.cc631 root_->type_ = IVL_SCT_MODULE; in add_root()
2505 scop->type_ = IVL_SCT_MODULE; in scope()
/dports/cad/iverilog/verilog-11.0/tgt-stub/
H A Dstub.c1706 case IVL_SCT_MODULE: in show_scope()
1876 case IVL_SCT_MODULE: in target_design()
/dports/cad/iverilog/verilog-11.0/tgt-vvp/
H A Dvvp_scope.c2274 case IVL_SCT_MODULE: type = "module"; break; in draw_scope()
2336 if( ivl_scope_type(net) == IVL_SCT_MODULE ) { in draw_scope()