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Searched refs:IVL_VT_QUEUE (Results 1 – 20 of 20) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-stub/
H A Dtypes.c69 case IVL_VT_QUEUE: in show_net_type()
127 case IVL_VT_QUEUE: in show_type_of_signal()
H A Dstub.c178 case IVL_VT_QUEUE: in data_type_string()
/dports/cad/iverilog/verilog-11.0/
H A Dnetqueue.cc36 return IVL_VT_QUEUE; in base_type()
H A Dnetmisc.cc1019 case IVL_VT_QUEUE: in elab_and_eval()
1022 if ((type == IVL_VT_DARRAY) || (type == IVL_VT_QUEUE)) in elab_and_eval()
H A Divl_target.h464 IVL_VT_QUEUE = 8, /* SystemVerilog queue instances */ enumerator
H A Delab_expr.cc112 case IVL_VT_QUEUE: in elaborate_rval_expr()
209 ntype->base_type()==IVL_VT_QUEUE)) { in elaborate_expr()
216 ntype->base_type()==IVL_VT_QUEUE) in elaborate_expr()
3026 case IVL_VT_QUEUE: in elaborate_expr()
3198 case IVL_VT_QUEUE: in calculate_packed_indices_()
H A Ddesign_dump.cc117 case IVL_VT_QUEUE: in operator <<()
H A Dt-dll.cc2706 if (obj->net_type->base_type() == IVL_VT_QUEUE) { in signal()
2716 (obj->net_type->base_type() == IVL_VT_QUEUE)); in signal()
H A Deval_tree.cc2156 case IVL_VT_QUEUE: in get_array_info()
/dports/cad/iverilog/verilog-11.0/tgt-vvp/
H A Deval_string.c113 … assert(ivl_signal_data_type(sig) == IVL_VT_DARRAY || ivl_signal_data_type(sig) == IVL_VT_QUEUE); in string_ex_select()
H A Ddraw_ufunc.c153 case IVL_VT_QUEUE: in draw_ufunc_preamble()
H A Deval_real.c263 … assert(ivl_signal_data_type(sig) == IVL_VT_DARRAY || ivl_signal_data_type(sig) == IVL_VT_QUEUE); in draw_select_real()
H A Dstmt_assign.c1133 assert(ivl_type_base(var_type) == IVL_VT_QUEUE); in show_stmt_assign_sig_queue()
1336 if (sig && (ivl_signal_data_type(sig) == IVL_VT_QUEUE)) { in show_stmt_assign()
H A Dvvp_process.c1760 if (ivl_type_base(ivl_signal_net_type(var)) != IVL_VT_QUEUE) in show_delete_method()
1782 assert(ivl_type_base(var_type) == IVL_VT_QUEUE); in show_insert_method()
1835 assert(ivl_type_base(var_type) == IVL_VT_QUEUE); in show_push_frontback_method()
H A Dvvp_scope.c548 } else if (ivl_signal_data_type(sig) == IVL_VT_QUEUE) { in draw_reg_in_scope()
2305 case IVL_VT_QUEUE: in draw_scope()
H A Deval_vec4.c946 || (ivl_signal_data_type(sig)==IVL_VT_QUEUE) ); in draw_select_vec4()
/dports/cad/iverilog/verilog-11.0/tgt-vlog95/
H A Dstmt.c99 if (ivl_type_base(net_type) == IVL_VT_QUEUE) { in emit_stmt_lval_name()
276 (ivl_signal_data_type(sig) == IVL_VT_QUEUE))) { in emit_stmt_lval_piece()
H A Dexpr.c889 (ivl_signal_data_type(ivl_expr_signal(sig_expr)) == IVL_VT_QUEUE))) { in emit_expr_select()
H A Dscope.c105 } else if (ivl_signal_data_type(sig) == IVL_VT_QUEUE) { in emit_var_def()
H A Dlogic_lpm.c2478 case IVL_VT_QUEUE: fprintf(stderr, " queue"); break; in dump_nexus_information()