1 /* 2 * Copyright (c) 1996, 1998 Gary Jennejohn. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 4. Altered versions must be plainly marked as such, and must not be 17 * misrepresented as being the original software and/or documentation. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 *--------------------------------------------------------------------------- 32 * 33 * $Id: isac.h,v 1.4 2011/08/07 20:05:08 jakllsch Exp $ 34 * 35 * last edit-date: [Sun Feb 14 10:27:13 1999] 36 * 37 * -hm split up for rewrite of Siemens chipset driver 38 * 39 *--------------------------------------------------------------------------- 40 */ 41 42 #ifndef I4B_ISAC_H_ 43 #define I4B_ISAC_H_ 44 45 /* 46 * The ISAC databook specifies a delay of 2.5 DCL clock cycles between 47 * writes to the ISAC command register CMDR. This is the delay used to 48 * satisfy this requirement. 49 */ 50 51 #define I4B_ISAC_CMDRWRDELAY 30 52 53 #if (I4B_ISAC_CMDRWRDELAY > 0) 54 #define ISACCMDRWRDELAY() DELAY(I4B_ISAC_CMDRWRDELAY) 55 #else 56 #warning "I4B_ISAC_CMDRWRDELAY set to 0!" 57 #define ISACCMDRWRDELAY() 58 #endif 59 60 enum ISAC_VERSIONS { 61 ISAC_VA, /* 2085 A1 or A2, 2086/2186 V1.1 */ 62 ISAC_VB1, /* 2085 B1 */ 63 ISAC_VB2, /* 2085 B2 */ 64 ISAC_VB3, /* 2085 B3/V2.3 */ 65 ISAC_UNKN /* unknown version */ 66 }; 67 68 #define ISAC_FIFO_LEN 32 /* 32 bytes FIFO on chip */ 69 70 /* 71 * definitions of registers and bits for the ISAC ISDN chip. 72 */ 73 74 typedef struct isac_reg { 75 76 /* 32 byte deep FIFO always first */ 77 78 unsigned char isac_fifo [ISAC_FIFO_LEN]; 79 80 /* most registers can be read/written, but have different names */ 81 /* so define a union with read/write names to make that clear */ 82 83 union { 84 struct { 85 unsigned char isac_ista; 86 unsigned char isac_star; 87 unsigned char isac_mode; 88 unsigned char isac_timr; 89 unsigned char isac_exir; 90 unsigned char isac_rbcl; 91 unsigned char isac_sapr; 92 unsigned char isac_rsta; 93 unsigned char dummy_28; 94 unsigned char isac_rhcr; 95 unsigned char isac_rbch; 96 unsigned char isac_star2; 97 unsigned char dummy_2c; 98 unsigned char dummy_2d; 99 unsigned char dummy_2e; 100 unsigned char dummt_2f; 101 unsigned char isac_spcr; 102 unsigned char isac_cirr; 103 unsigned char isac_mor; 104 unsigned char isac_sscr; 105 unsigned char isac_sfcr; 106 unsigned char isac_c1r; 107 unsigned char isac_c2r; 108 unsigned char isac_b1cr; 109 unsigned char isac_b2cr; 110 unsigned char isac_adf2; 111 unsigned char isac_mosr; 112 unsigned char isac_sqrr; 113 } isac_r; 114 struct { 115 unsigned char isac_mask; 116 unsigned char isac_cmdr; 117 unsigned char isac_mode; 118 unsigned char isac_timr; 119 unsigned char isac_xad1; 120 unsigned char isac_xad2; 121 unsigned char isac_sap1; 122 unsigned char isac_sap2; 123 unsigned char isac_tei1; 124 unsigned char isac_tei2; 125 unsigned char dummy_2a; 126 unsigned char isac_star2; 127 unsigned char dummy_2c; 128 unsigned char dummy_2d; 129 unsigned char dummy_2e; 130 unsigned char dummt_2f; 131 unsigned char isac_spcr; 132 unsigned char isac_cixr; 133 unsigned char isac_mox; 134 unsigned char isac_sscx; 135 unsigned char isac_sfcw; 136 unsigned char isac_c1r; 137 unsigned char isac_c2r; 138 unsigned char isac_stcr; 139 unsigned char isac_adf1; 140 unsigned char isac_adf2; 141 unsigned char isac_mocr; 142 unsigned char isac_sqxr; 143 } isac_w; 144 } isac_rw; 145 } isac_reg_t; 146 147 #define REG_OFFSET(type, field) (uintptr_t)(&(((type *)0)->field)) 148 149 /* ISAC read registers */ 150 151 #define i_ista isac_rw.isac_r.isac_ista 152 #define I_ISTA REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_ista) 153 #define i_star isac_rw.isac_r.isac_star 154 #define I_STAR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_star) 155 #define i_mode isac_rw.isac_r.isac_mode 156 #define I_MODE REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mode) 157 #define i_timr isac_rw.isac_r.isac_timr 158 #define I_TIMR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_timr) 159 #define i_exir isac_rw.isac_r.isac_exir 160 #define I_EXIR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_exir) 161 #define i_rbcl isac_rw.isac_r.isac_rbcl 162 #define I_RBCL REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rbcl) 163 #define i_sapr isac_rw.isac_r.isac_sapr 164 #define I_SAPR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sapr) 165 #define i_rsta isac_rw.isac_r.isac_rsta 166 #define I_RSTA REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rsta) 167 #define i_rhcr isac_rw.isac_r.isac_rhcr 168 #define I_RHCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rhcr) 169 #define i_rbch isac_rw.isac_r.isac_rbch 170 #define I_RBCH REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rbch) 171 #define i_star2 isac_rw.isac_r.isac_star2 172 #define I_STAR2 REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_star2) 173 #define i_spcr isac_rw.isac_r.isac_spcr 174 #define I_SPCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_spcr) 175 #define i_cirr isac_rw.isac_r.isac_cirr 176 #define I_CIRR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_cirr) 177 #define i_mor isac_rw.isac_r.isac_mor 178 #define I_MOR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mor) 179 #define i_sscr isac_rw.isac_r.isac_sscr 180 #define I_SSCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sscr) 181 #define i_sfcr isac_rw.isac_r.isac_sfcr 182 #define I_SFCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sfcr) 183 #define i_c1r isac_rw.isac_r.isac_c1r 184 #define I_C1R REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_c1r) 185 #define i_c2r isac_rw.isac_r.isac_c2r 186 #define I_C2R REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_c2r) 187 #define i_b1cr isac_rw.isac_r.isac_b1cr 188 #define I_B1CR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_b1cr) 189 #define i_b2cr isac_rw.isac_r.isac_b2cr 190 #define I_B2CR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_b2cr) 191 #define i_adf2 isac_rw.isac_r.isac_adf2 192 #define I_ADF2 REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_adf2) 193 #define i_mosr isac_rw.isac_r.isac_mosr 194 #define I_MOSR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mosr) 195 #define i_sqrr isac_rw.isac_r.isac_sqrr 196 #define I_SQRR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sqrr) 197 198 /* ISAC write registers - isac_mode, isac_timr, isac_star2, isac_spcr, */ 199 /* isac_c1r, isac_c2r, isac_adf2 see read registers */ 200 201 #define i_mask isac_rw.isac_w.isac_mask 202 #define I_MASK REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mask) 203 #define i_cmdr isac_rw.isac_w.isac_cmdr 204 #define I_CMDR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_cmdr) 205 #define i_xad1 isac_rw.isac_w.isac_xad1 206 #define I_XAD1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_xad1) 207 #define i_xad2 isac_rw.isac_w.isac_xad2 208 #define I_XAD2 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_xad2) 209 #define i_sap1 isac_rw.isac_w.isac_sap1 210 #define I_SAP1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sap1) 211 #define i_sap2 isac_rw.isac_w.isac_sap2 212 #define I_SAP2 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sap2) 213 #define i_tei1 isac_rw.isac_w.isac_tei1 214 #define i_tei2 isac_rw.isac_w.isac_tei2 215 #define i_cixr isac_rw.isac_w.isac_cixr 216 #define I_CIXR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_cixr) 217 #define I_CIX0 I_CIXR 218 #define i_mox isac_rw.isac_w.isac_mox 219 #define I_MOX REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mox) 220 #define i_sscx isac_rw.isac_w.isac_sscx 221 #define I_SSCX REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sscx) 222 #define i_sfcw isac_rw.isac_w.isac_sfcw 223 #define I_SFCW REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sfcw) 224 #define i_stcr isac_rw.isac_w.isac_stcr 225 #define I_STCR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_stcr) 226 #define i_adf1 isac_rw.isac_w.isac_adf1 227 #define I_ADF1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_adf1) 228 #define i_mocr isac_rw.isac_w.isac_mocr 229 #define I_MOCR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mocr) 230 #define i_sqxr isac_rw.isac_w.isac_sqxr 231 #define I_SQXR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sqxr) 232 233 #define ISAC_ISTA_RME 0x80 234 #define ISAC_ISTA_RPF 0x40 235 #define ISAC_ISTA_RSC 0x20 236 #define ISAC_ISTA_XPR 0x10 237 #define ISAC_ISTA_TIN 0x08 238 #define ISAC_ISTA_CISQ 0x04 239 #define ISAC_ISTA_SIN 0x02 240 #define ISAC_ISTA_EXI 0x01 241 242 #define ISAC_MASK_RME 0x80 243 #define ISAC_MASL_RPF 0x40 244 #define ISAC_MASK_RSC 0x20 245 #define ISAC_MASK_XPR 0x10 246 #define ISAC_MASK_TIN 0x08 247 #define ISAC_MASK_CISQ 0x04 248 #define ISAC_MASK_SIN 0x02 249 #define ISAC_MASK_EXI 0x01 250 #define ISAC_MASK_ALL 0xff 251 252 #define ISAC_STAR_XDOV 0x80 253 #define ISAC_STAR_XFW 0x40 254 #define ISAC_STAR_XRNR 0x20 255 #define ISAC_STAR_RRNR 0x10 256 #define ISAC_STAR_MBR 0x08 257 #define ISAC_STAR_MAC1 0x04 258 #define ISAC_STAR_BVS 0x02 259 #define ISAC_STAR_MAC0 0x01 260 261 #define ISAC_CMDR_RMC 0x80 262 #define ISAC_CMDR_RRES 0x40 263 #define ISAC_CMDR_RNR 0x20 264 #define ISAC_CMDR_STI 0x10 265 #define ISAC_CMDR_XTF 0x08 266 #define ISAC_CMDR_XIF 0x04 267 #define ISAC_CMDR_XME 0x02 268 #define ISAC_CMDR_XRES 0x01 269 270 #define ISAC_MODE_MDS2 0x80 271 #define ISAC_MODE_MDS1 0x40 272 #define ISAC_MODE_MDS0 0x20 273 #define ISAC_MODE_TMD 0x10 274 #define ISAC_MODE_RAC 0x08 275 #define ISAC_MODE_DIM2 0x04 276 #define ISAC_MODE_DIM1 0x02 277 #define ISAC_MODE_DIM0 0x01 278 279 #define ISAC_EXIR_XMR 0x80 280 #define ISAC_EXIR_XDU 0x40 281 #define ISAC_EXIR_PCE 0x20 282 #define ISAC_EXIR_RFO 0x10 283 #define ISAC_EXIR_SOV 0x08 284 #define ISAC_EXIR_MOS 0x04 285 #define ISAC_EXIR_SAW 0x02 286 #define ISAC_EXIR_WOV 0x01 287 288 #define ISAC_RSTA_RDA 0x80 289 #define ISAC_RSTA_RDO 0x40 290 #define ISAC_RSTA_CRC 0x20 291 #define ISAC_RSTA_RAB 0x10 292 #define ISAC_RSTA_SA1 0x08 293 #define ISAC_RSTA_SA0 0x04 294 #define ISAC_RSTA_CR 0x02 295 #define ISAC_RSTA_TA 0x01 296 297 #define ISAC_RSTA_MASK 0x70 /* the interesting bits */ 298 299 #define ISAC_RBCH_XAC 0x80 300 #define ISAC_RBCH_VN1 0x40 301 #define ISAC_RBCH_VN0 0x20 302 #define ISAC_RBCH_OV 0x10 303 /* the other 4 bits are the high bits of the receive byte count */ 304 305 #define ISAC_SPCR_SPU 0x80 306 #define ISAC_SPCR_SAC 0x40 307 #define ISAC_SPCR_SPM 0x20 308 #define ISAC_SPCR_TLP 0x10 309 #define ISAC_SPCR_C1C1 0x08 310 #define ISAC_SPCR_C1C0 0x04 311 #define ISAC_SPCR_C2C1 0x02 312 #define ISAC_SPCR_C2C0 0x01 313 314 #define ISAC_CIRR_SQC 0x80 315 #define ISAC_CIRR_BAS 0x40 316 /* bits 5-2 CODR */ 317 #define ISAC_CIRR_CIC0 0x02 318 /* bit 0 is always 0 */ 319 /* C/I codes from bits 5-2 (>> 2 & 0xf) */ 320 /* the indications */ 321 #define ISAC_CIRR_IPU 0x07 322 #define ISAC_CIRR_IDR 0x00 323 #define ISAC_CIRR_ISD 0x02 324 #define ISAC_CIRR_IDIS 0x03 325 #define ISAC_CIRR_IEI 0x06 326 #define ISAC_CIRR_IRSY 0x04 327 #define ISAC_CIRR_IARD 0x08 328 #define ISAC_CIRR_ITI 0x0a 329 #define ISAC_CIRR_IATI 0x0b 330 #define ISAC_CIRR_IAI8 0x0c 331 #define ISAC_CIRR_IAI10 0x0d 332 #define ISAC_CIRR_IDID 0x0f 333 334 #define ISAC_CI_MASK 0x0f 335 336 #define ISAC_CIXR_RSS 0x80 337 #define ISAC_CIXR_BAC 0x40 338 /* bits 5-2 CODX */ 339 #define ISAC_CIXR_TCX 0x02 340 #define ISAC_CIXR_ECX 0x01 341 /* in IOM-2 mode the low bits are always 1 */ 342 #define ISAC_CIX0_LOW 0x03 343 /* C/I codes from bits 5-2 (>> 2 & 0xf) */ 344 /* the commands */ 345 #define ISAC_CIXR_CTIM 0 346 #define ISAC_CIXR_CRS 0x01 347 #define ISAC_CIXR_CSCZ 0x04 348 #define ISAC_CIXR_CSSZ 0x02 349 #define ISAC_CIXR_CAR8 0x08 350 #define ISAC_CIXR_CAR10 0x09 351 #define ISAC_CIXR_CARL 0x0a 352 #define ISAC_CIXR_CDIU 0x0f 353 354 #define ISAC_STCR_TSF 0x80 355 #define ISAC_STCR_TBA2 0x40 356 #define ISAC_STCR_TBA1 0x20 357 #define ISAC_STCR_TBA0 0x10 358 #define ISAC_STCR_ST1 0x08 359 #define ISAC_STCR_ST0 0x04 360 #define ISAC_STCR_SC1 0x02 361 #define ISAC_STCR_SC0 0x01 362 363 #define ISAC_ADF1_WTC1 0x80 364 #define ISAC_ADF1_WTC2 0x40 365 #define ISAC_ADF1_TEM 0x20 366 #define ISAC_ADF1_PFS 0x10 367 #define ISAC_ADF1_CFS 0x08 368 #define ISAC_ADF1_FC2 0x04 369 #define ISAC_ADF1_FC1 0x02 370 #define ISAC_ADF1_ITF 0x01 371 372 #define ISAC_ADF2_IMS 0x80 373 /* all other bits are 0 */ 374 375 /* bits 7-5 are always 0 */ 376 #define ISAC_SQRR_SYN 0x10 377 #define ISAC_SQRR_SQR1 0x08 378 #define ISAC_SQRR_SQR2 0x04 379 #define ISAC_SQRR_SQR3 0x02 380 #define ISAC_SQRR_SQR4 0x01 381 382 #define ISAC_SQXR_IDC 0x80 383 #define ISAC_SQXR_CFS 0x40 384 #define ISAC_SQXR_CI1E 0x20 385 #define ISAC_SQXR_SQIE 0x10 386 #define ISAC_SQXR_SQX1 0x08 387 #define ISAC_SQXR_SQX2 0x04 388 #define ISAC_SQXR_SQX3 0x02 389 #define ISAC_SQXR_SQX4 0x01 390 391 #endif /* I4B_ISAC_H_ */ 392