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/dports/misc/veles/veles-2018.05.0/python/veles/dis/isa/
H A Dfalcon.py21 from ..insn import InsnSwitch, Insn
496 IsaMatch(0, Insn("not", args.r1s)),
497 IsaMatch(1, Insn("neg", args.r1s)),
630 IsaMatch(0, Insn("ret")),
631 IsaMatch(1, Insn("iret")),
632 IsaMatch(2, Insn("halt")),
633 IsaMatch(3, Insn("xdwait")),
634 IsaMatch(6, Insn("xdbar")),
635 IsaMatch(7, Insn("xcwait")),
645 IsaMatch(4, Insn("jmp", args.r1)),
[all …]
/dports/textproc/jade/jade-1.2.1/style/
H A DInsn.h21 class Insn : public Resource {
23 virtual ~Insn();
29 typedef ConstPtr<Insn> InsnPtr;
31 class ErrorInsn : public Insn {
79 class OrInsn : public Insn {
344 virtual const Insn *call(VM &vm, const Location &, const Insn *next) = 0;
360 const Insn *call(VM &vm, const Location &, const Insn *next);
377 const Insn *call(VM &vm, const Location &, const Insn *next);
387 const Insn *call(VM &vm, const Location &, const Insn *next);
401 const Insn *call(VM &, const Location &, const Insn *);
[all …]
/dports/textproc/openjade/openjade-1.3.3-pre1/style/
H A DInsn.h21 class Insn : public Resource {
23 virtual ~Insn();
29 typedef ConstPtr<Insn> InsnPtr;
31 class ErrorInsn : public Insn { in VM()
79 class OrInsn : public Insn {
344 virtual const Insn *call(VM &vm, const Location &, const Insn *next) = 0;
360 const Insn *call(VM &vm, const Location &, const Insn *next);
377 const Insn *call(VM &vm, const Location &, const Insn *next);
387 const Insn *call(VM &vm, const Location &, const Insn *next); in ApplyInsn()
401 const Insn *call(VM &, const Location &, const Insn *);
[all …]
/dports/devel/capstone4/capstone-4.0.2/arch/XCore/
H A DXCoreDisassembler.c198 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
203 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
218 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
222 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
242 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
313 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
413 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
414 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
655 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
692 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/devel/capstone3/capstone-3.0.5/arch/XCore/
H A DXCoreDisassembler.c195 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
200 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
215 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
219 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
239 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
310 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
410 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
411 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
652 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
689 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/capstone/arch/XCore/
H A DXCoreDisassembler.c195 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
200 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
215 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
219 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
239 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
310 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
410 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
411 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
652 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
689 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/emulators/qemu/qemu-6.2.0/capstone/arch/XCore/
H A DXCoreDisassembler.c198 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
203 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
218 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
222 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
242 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
313 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
413 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
414 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
655 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
692 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/capstone/arch/XCore/
H A DXCoreDisassembler.c198 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
203 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
218 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
222 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
242 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
313 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
413 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
414 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
655 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
692 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/capstone/arch/XCore/
H A DXCoreDisassembler.c195 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
200 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
215 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
219 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
239 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
310 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
410 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
411 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
652 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
689 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/devel/py-capstone/capstone-4.0.1/src/arch/XCore/
H A DXCoreDisassembler.c196 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
201 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
216 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
220 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
240 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
311 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
411 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
412 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
653 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
690 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/capstone/arch/XCore/
H A DXCoreDisassembler.c198 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
203 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
218 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
222 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
242 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
313 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
413 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
414 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
655 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
692 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/devel/redasm/REDasm-2.1.1/LibREDasm/depends/capstone/arch/XCore/
H A DXCoreDisassembler.c196 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
201 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
216 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
220 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
240 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
311 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
411 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
412 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
653 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
690 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/capstone/arch/XCore/
H A DXCoreDisassembler.c195 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
200 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
215 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
219 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
239 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
310 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
410 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
411 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
652 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
689 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/capstone/arch/XCore/
H A DXCoreDisassembler.c195 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
200 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
215 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
219 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
239 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
310 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
410 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
411 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
652 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
689 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/devel/xelfviewer/XELFViewer-0.03/XCapstone/3rdparty/Capstone/src/arch/XCore/
H A DXCoreDisassembler.c198 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode2OpInstruction()
203 if (fieldFromInstruction_4(Insn, 5, 1)) { in Decode2OpInstruction()
218 static DecodeStatus Decode3OpInstruction(unsigned Insn, in Decode3OpInstruction() argument
222 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); in Decode3OpInstruction()
242 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); in Decode2OpInstructionFail()
313 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
413 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | in DecodeL2OpInstructionFail()
414 fieldFromInstruction_4(Insn, 27, 5) << 4; in DecodeL2OpInstructionFail()
655 Opcode = fieldFromInstruction_4(Insn, 27, 5); in DecodeL5RInstructionFail()
692 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
92 unsigned Insn,
102 unsigned Insn,
112 unsigned Insn,
127 unsigned Insn,
137 unsigned Insn,
157 unsigned Insn,
244 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
92 unsigned Insn,
102 unsigned Insn,
112 unsigned Insn,
127 unsigned Insn,
137 unsigned Insn,
157 unsigned Insn,
244 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
92 unsigned Insn,
102 unsigned Insn,
112 unsigned Insn,
127 unsigned Insn,
137 unsigned Insn,
157 unsigned Insn,
244 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
92 unsigned Insn,
102 unsigned Insn,
112 unsigned Insn,
127 unsigned Insn,
137 unsigned Insn,
157 unsigned Insn,
244 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
92 unsigned Insn,
102 unsigned Insn,
112 unsigned Insn,
127 unsigned Insn,
137 unsigned Insn,
157 unsigned Insn,
244 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
92 unsigned Insn,
102 unsigned Insn,
112 unsigned Insn,
127 unsigned Insn,
137 unsigned Insn,
157 unsigned Insn,
244 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
92 unsigned Insn,
102 unsigned Insn,
112 unsigned Insn,
127 unsigned Insn,
137 unsigned Insn,
157 unsigned Insn,
244 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
92 unsigned Insn,
102 unsigned Insn,
112 unsigned Insn,
127 unsigned Insn,
137 unsigned Insn,
157 unsigned Insn,
244 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
92 unsigned Insn,
102 unsigned Insn,
112 unsigned Insn,
127 unsigned Insn,
137 unsigned Insn,
157 unsigned Insn,
244 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
92 unsigned Insn,
102 unsigned Insn,
112 unsigned Insn,
127 unsigned Insn,
137 unsigned Insn,
157 unsigned Insn,
244 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]

12345678910>>...82