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Searched refs:LCCR2_VSW (Results 1 – 25 of 150) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/mach-pxa/include/mach/
H A Dregs-lcd.h104 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */ macro
105 #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm/mach-pxa/include/mach/
H A Dregs-lcd.h104 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */ macro
105 #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm/mach-pxa/include/mach/
H A Dregs-lcd.h104 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */ macro
105 #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/devel/openwince-include/include-0.4.2/arm/pxa2x0/
H A Dlcd.h173 #define LCCR2_VSW(x) bits_val(15,10,x) macro
/dports/multimedia/libv4l/linux-5.13-rc2/Documentation/fb/
H A Dpxafb.rst45 vsynclen:VSYNC == LCCR2_VSW + 1
/dports/multimedia/v4l-utils/linux-5.13-rc2/Documentation/fb/
H A Dpxafb.rst45 vsynclen:VSYNC == LCCR2_VSW + 1
/dports/multimedia/v4l_compat/linux-5.13-rc2/Documentation/fb/
H A Dpxafb.rst45 vsynclen:VSYNC == LCCR2_VSW + 1
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1734 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
1738 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1734 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
1738 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1734 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
1738 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ macro
2164 (((Tln) - 1) << FShft (LCCR2_VSW))

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