Home
last modified time | relevance | path

Searched refs:LEVEL0_MPLL_POST_DIV_MASK (Results 1 – 8 of 8) sorted by relevance

/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv6xxd.h80 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0) macro
H A Drv6xx_dpm.c383 LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK); in rv6xx_memory_clock_entry_set_post_divider()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Drv6xxd.h80 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0) macro
H A Drv6xx_dpm.c383 LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK); in rv6xx_memory_clock_entry_set_post_divider()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Drv6xxd.h80 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0) macro
H A Drv6xx_dpm.c383 LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK); in rv6xx_memory_clock_entry_set_post_divider()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Drv6xxd.h80 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0) macro
H A Drv6xx_dpm.c383 LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK); in rv6xx_memory_clock_entry_set_post_divider()