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Searched refs:LUT_I1 (Results 1 – 3 of 3) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-fpga/
H A Dd-virtex.c111 edif_add_to_joint(jnt, lut, LUT_I1); in virtex_or_wide()
159 edif_add_to_joint(jnt, lut, LUT_I1); in virtex_or_wide()
171 edif_add_to_joint(jnt, lut, LUT_I1); in virtex_or_wide()
186 edif_add_to_joint(jnt, lut, LUT_I1); in virtex_or_wide()
379 edif_add_to_joint(jnt, lut, LUT_I1); in virtex_eq()
393 edif_add_to_joint(jnt, lut, LUT_I1); in virtex_eq()
432 edif_add_to_joint(jnt, lut, LUT_I1); in virtex_eq()
500 edif_add_to_joint(jnt, lut, LUT_I1); in virtex_ge()
544 edif_add_to_joint(jnt, lut, LUT_I1); in virtex_ge()
618 edif_add_to_joint(jnt, lut, LUT_I1); in virtex_ge()
[all …]
H A Dxilinx.c143 edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT); in xilinx_cell_lut2()
155 edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT); in xilinx_cell_lut3()
168 edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT); in xilinx_cell_lut4()
580 edif_add_to_joint(jnt, lut, LUT_I1); in lut_logic()
743 edif_add_to_joint(jnt, lut, LUT_I1); in xilinx_mux()
787 edif_add_to_joint(jnt, lut, LUT_I1); in xilinx_add()
897 edif_add_to_joint(jnt1, table[0][qdx], LUT_I1); in xilinx_shiftl()
914 edif_add_to_joint(jnt1, table[sdx][qdx], LUT_I1); in xilinx_shiftl()
H A Dxilinx.h60 #define LUT_I1 2 macro