| /dports/devel/avr-gdb/gdb-7.3.1/sim/m32r/ |
| H A D | decode2.h | 39 , M32R2F_INSN_AND, M32R2F_INSN_AND3, M32R2F_INSN_OR, M32R2F_INSN_OR3 enumerator
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| H A D | decode2.c | 55 { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND },
303 case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add; in m32r2f_decode()
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| H A D | model2.c | 3049 { M32R2F_INSN_AND, model_m32r2_and, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
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| H A D | sem2-switch.c | 43 { M32R2F_INSN_AND, && case_sem_INSN_AND },
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| /dports/devel/gdb761/gdb-7.6.1/sim/m32r/ |
| H A D | decode2.h | 38 , M32R2F_INSN_AND, M32R2F_INSN_AND3, M32R2F_INSN_OR, M32R2F_INSN_OR3 enumerator
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| H A D | decode2.c | 54 { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND },
302 case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add; in m32r2f_decode()
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| H A D | model2.c | 3048 { M32R2F_INSN_AND, model_m32r2_and, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
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| H A D | sem2-switch.c | 42 { M32R2F_INSN_AND, && case_sem_INSN_AND },
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| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/ |
| H A D | decode2.h | 39 , M32R2F_INSN_AND, M32R2F_INSN_AND3, M32R2F_INSN_OR, M32R2F_INSN_OR3 enumerator
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| H A D | decode2.c | 55 { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND },
296 case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add;
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| H A D | model2.c | 3049 { M32R2F_INSN_AND, model_m32r2_and, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
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| H A D | sem2-switch.c | 43 { M32R2F_INSN_AND, && case_sem_INSN_AND },
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| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/ |
| H A D | decode2.h | 39 , M32R2F_INSN_AND, M32R2F_INSN_AND3, M32R2F_INSN_OR, M32R2F_INSN_OR3 enumerator
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| H A D | decode2.c | 55 { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND },
296 case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add; in m32r2f_decode()
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| H A D | model2.c | 3049 { M32R2F_INSN_AND, model_m32r2_and, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
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| H A D | sem2-switch.c | 43 { M32R2F_INSN_AND, && case_sem_INSN_AND },
|