| /dports/devel/avr-gdb/gdb-7.3.1/sim/m32r/ |
| H A D | decode2.h | 50 , M32R2F_INSN_DIVUH, M32R2F_INSN_DIVB, M32R2F_INSN_DIVUB, M32R2F_INSN_DIVH enumerator
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| H A D | decode2.c | 99 { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
591 { itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div; } in m32r2f_decode()
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| H A D | model2.c | 3093 { M32R2F_INSN_DIVUH, model_m32r2_divuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
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| H A D | sem2-switch.c | 87 { M32R2F_INSN_DIVUH, && case_sem_INSN_DIVUH },
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| /dports/devel/gdb761/gdb-7.6.1/sim/m32r/ |
| H A D | decode2.h | 49 , M32R2F_INSN_DIVUH, M32R2F_INSN_DIVB, M32R2F_INSN_DIVUB, M32R2F_INSN_DIVH enumerator
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| H A D | decode2.c | 98 { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
590 { itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div; } in m32r2f_decode()
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| H A D | model2.c | 3092 { M32R2F_INSN_DIVUH, model_m32r2_divuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
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| H A D | sem2-switch.c | 86 { M32R2F_INSN_DIVUH, && case_sem_INSN_DIVUH },
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| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/ |
| H A D | decode2.h | 50 , M32R2F_INSN_DIVUH, M32R2F_INSN_DIVB, M32R2F_INSN_DIVUB, M32R2F_INSN_DIVH enumerator
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| H A D | decode2.c | 99 { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
510 case 2 : itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div;
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| H A D | model2.c | 3093 { M32R2F_INSN_DIVUH, model_m32r2_divuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
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| H A D | sem2-switch.c | 87 { M32R2F_INSN_DIVUH, && case_sem_INSN_DIVUH },
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| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/ |
| H A D | decode2.h | 50 , M32R2F_INSN_DIVUH, M32R2F_INSN_DIVB, M32R2F_INSN_DIVUB, M32R2F_INSN_DIVH enumerator
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| H A D | decode2.c | 99 { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
510 case 2 : itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div; in m32r2f_decode()
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| H A D | model2.c | 3093 { M32R2F_INSN_DIVUH, model_m32r2_divuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
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| H A D | sem2-switch.c | 87 { M32R2F_INSN_DIVUH, && case_sem_INSN_DIVUH },
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