| /dports/emulators/qemu/qemu-6.2.0/hw/ppc/ |
| H A D | ppc4xx_devs.c | 507 MAL0_RCBS0 = 0x1E0, enumerator
598 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_read_mal()
599 ret = mal->rcbs[dcrn - MAL0_RCBS0]; in dcr_read_mal()
659 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_write_mal()
660 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; in dcr_write_mal()
712 ppc_dcr_register(env, MAL0_RCBS0 + i, in ppc4xx_mal_init()
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| /dports/emulators/qemu60/qemu-6.0.0/hw/ppc/ |
| H A D | ppc4xx_devs.c | 508 MAL0_RCBS0 = 0x1E0, enumerator
599 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_read_mal()
600 ret = mal->rcbs[dcrn - MAL0_RCBS0]; in dcr_read_mal()
660 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_write_mal()
661 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; in dcr_write_mal()
713 ppc_dcr_register(env, MAL0_RCBS0 + i, in ppc4xx_mal_init()
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| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/ppc/ |
| H A D | ppc4xx_devs.c | 507 MAL0_RCBS0 = 0x1E0,
598 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
599 ret = mal->rcbs[dcrn - MAL0_RCBS0];
659 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
660 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;
712 ppc_dcr_register(env, MAL0_RCBS0 + i,
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| /dports/emulators/qemu42/qemu-4.2.1/hw/ppc/ |
| H A D | ppc4xx_devs.c | 749 MAL0_RCBS0 = 0x1E0, enumerator
840 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_read_mal()
841 ret = mal->rcbs[dcrn - MAL0_RCBS0]; in dcr_read_mal()
901 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_write_mal()
902 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; in dcr_write_mal()
954 ppc_dcr_register(env, MAL0_RCBS0 + i, in ppc4xx_mal_init()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/hw/ppc/ |
| H A D | ppc4xx_devs.c | 749 MAL0_RCBS0 = 0x1E0, enumerator
840 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_read_mal()
841 ret = mal->rcbs[dcrn - MAL0_RCBS0]; in dcr_read_mal()
901 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_write_mal()
902 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; in dcr_write_mal()
954 ppc_dcr_register(env, MAL0_RCBS0 + i, in ppc4xx_mal_init()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/ppc/ |
| H A D | ppc4xx_devs.c | 748 MAL0_RCBS0 = 0x1E0, enumerator
839 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_read_mal()
840 ret = mal->rcbs[dcrn - MAL0_RCBS0]; in dcr_read_mal()
900 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_write_mal()
901 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; in dcr_write_mal()
953 ppc_dcr_register(env, MAL0_RCBS0 + i, in ppc4xx_mal_init()
|
| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/ppc/ |
| H A D | ppc4xx_devs.c | 748 MAL0_RCBS0 = 0x1E0, enumerator
839 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_read_mal()
840 ret = mal->rcbs[dcrn - MAL0_RCBS0]; in dcr_read_mal()
900 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_write_mal()
901 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; in dcr_write_mal()
953 ppc_dcr_register(env, MAL0_RCBS0 + i, in ppc4xx_mal_init()
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/ppc/ |
| H A D | ppc4xx_devs.c | 752 MAL0_RCBS0 = 0x1E0, enumerator
843 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_read_mal()
844 ret = mal->rcbs[dcrn - MAL0_RCBS0]; in dcr_read_mal()
904 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_write_mal()
905 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; in dcr_write_mal()
957 ppc_dcr_register(env, MAL0_RCBS0 + i, in ppc4xx_mal_init()
|
| /dports/emulators/qemu5/qemu-5.2.0/hw/ppc/ |
| H A D | ppc4xx_devs.c | 748 MAL0_RCBS0 = 0x1E0, enumerator
839 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_read_mal()
840 ret = mal->rcbs[dcrn - MAL0_RCBS0]; in dcr_read_mal()
900 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { in dcr_write_mal()
901 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; in dcr_write_mal()
953 ppc_dcr_register(env, MAL0_RCBS0 + i, in ppc4xx_mal_init()
|
| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/include/asm/ |
| H A D | ppc4xx-mal.h | 49 #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | ether.c | 199 mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16); in ether_post_init()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | ether.c | 199 mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16); in ether_post_init()
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | ether.c | 199 mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16); in ether_post_init()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | ether.c | 199 mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16); in ether_post_init()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | ether.c | 199 mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16); in ether_post_init()
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | ether.c | 199 mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16); in ether_post_init()
|
| /dports/sysutils/u-boot-utilite/u-boot-2015.07/post/cpu/ppc4xx/ |
| H A D | ether.c | 190 mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16); in ether_post_init()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | ether.c | 199 mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16); in ether_post_init()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 560 #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 560 #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 560 #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ macro
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 560 #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 560 #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ macro
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 560 #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 560 #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ macro
|