| /dports/devel/radare2/radare2-5.1.1/libr/asm/arch/riscv/ |
| H A D | riscv-opc.h | 149 #define MASK_MULHSU 0xfe00707f macro
845 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
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| H A D | riscv-opc.c | 398 {"mulhsu", "M", "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
|
| /dports/lang/sdcc/sdcc-4.0.0/support/sdbinutils/include/opcode/ |
| H A D | riscv-opc.h | 149 #define MASK_MULHSU 0xfe00707f macro
898 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
|
| /dports/devel/binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 173 #define MASK_MULHSU 0xfe00707f macro
946 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
|
| /dports/devel/arm-elf-binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 173 #define MASK_MULHSU 0xfe00707f macro
946 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
|
| /dports/devel/gnulibiberty/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 173 #define MASK_MULHSU 0xfe00707f macro
946 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
|
| /dports/devel/gdb/gdb-11.1/include/opcode/ |
| H A D | riscv-opc.h | 173 #define MASK_MULHSU 0xfe00707f macro
946 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
|
| /dports/devel/openocd/openocd-0.11.0/src/target/riscv/ |
| H A D | encoding.h | 435 #define MASK_MULHSU 0xfe00707f macro
2140 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
|
| /dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
| H A D | riscv-opc.c | 495 {"mulhsu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
|
| /dports/devel/gdb/gdb-11.1/opcodes/ |
| H A D | riscv-opc.c | 495 {"mulhsu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
|
| /dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
| H A D | riscv-opc.c | 495 {"mulhsu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
|
| /dports/devel/binutils/binutils-2.37/opcodes/ |
| H A D | riscv-opc.c | 495 {"mulhsu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
|
| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
| H A D | encoding.h | 437 #define MASK_MULHSU 0xfe00707f macro
3171 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
|