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Searched refs:MASK_OP_RRR2_S1 (Results 1 – 18 of 18) sorted by relevance

/dports/emulators/qemu-utils/qemu-4.2.1/target/tricore/
H A Dtricore-opcodes.h253 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op) macro
H A Dtranslate.c7169 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_madd()
7221 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_msub()
/dports/emulators/qemu5/qemu-5.2.0/target/tricore/
H A Dtricore-opcodes.h253 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op) macro
H A Dtranslate.c7173 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_madd()
7225 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_msub()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/tricore/
H A Dtricore-opcodes.h253 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op) macro
H A Dtranslate.c7169 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_madd()
7221 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_msub()
/dports/emulators/qemu42/qemu-4.2.1/target/tricore/
H A Dtricore-opcodes.h253 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op) macro
H A Dtranslate.c7169 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_madd()
7221 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_msub()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/tricore/
H A Dtricore-opcodes.h250 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op) macro
H A Dtranslate.c7182 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_madd()
7234 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_msub()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/tricore/
H A Dtricore-opcodes.h253 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op) macro
H A Dtranslate.c7169 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_madd()
7221 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_msub()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/tricore/
H A Dtricore-opcodes.h253 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op) macro
H A Dtranslate.c7172 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_madd()
7224 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_msub()
/dports/emulators/qemu/qemu-6.2.0/target/tricore/
H A Dtricore-opcodes.h253 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op) macro
H A Dtranslate.c7160 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_madd()
7212 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_msub()
/dports/emulators/qemu60/qemu-6.0.0/target/tricore/
H A Dtricore-opcodes.h253 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op) macro
H A Dtranslate.c7184 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_madd()
7236 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_msub()