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Searched refs:MASK_OP_RRR_S2 (Results 1 – 18 of 18) sorted by relevance

/dports/emulators/qemu-utils/qemu-4.2.1/target/tricore/
H A Dtricore-opcodes.h237 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) macro
H A Dtranslate.c7045 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_cond_select()
7091 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_divide()
/dports/emulators/qemu5/qemu-5.2.0/target/tricore/
H A Dtricore-opcodes.h237 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) macro
H A Dtranslate.c7049 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_cond_select()
7095 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_divide()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/tricore/
H A Dtricore-opcodes.h237 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) macro
H A Dtranslate.c7045 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_cond_select()
7091 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_divide()
/dports/emulators/qemu42/qemu-4.2.1/target/tricore/
H A Dtricore-opcodes.h237 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) macro
H A Dtranslate.c7045 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_cond_select()
7091 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_divide()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/tricore/
H A Dtricore-opcodes.h234 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) macro
H A Dtranslate.c7058 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_cond_select()
7104 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_divide()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/tricore/
H A Dtricore-opcodes.h237 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) macro
H A Dtranslate.c7045 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_cond_select()
7091 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_divide()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/tricore/
H A Dtricore-opcodes.h237 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) macro
H A Dtranslate.c7048 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_cond_select()
7094 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_divide()
/dports/emulators/qemu/qemu-6.2.0/target/tricore/
H A Dtricore-opcodes.h237 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) macro
H A Dtranslate.c7036 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_cond_select()
7082 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_divide()
/dports/emulators/qemu60/qemu-6.0.0/target/tricore/
H A Dtricore-opcodes.h237 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) macro
H A Dtranslate.c7060 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_cond_select()
7106 r2 = MASK_OP_RRR_S2(ctx->opcode); in decode_rrr_divide()