| /dports/devel/radare2/radare2-5.1.1/libr/asm/arch/riscv/ |
| H A D | riscv-opc.c | 559 {"fdiv.q", "Q", "D,S,T", MATCH_FDIV_Q | MASK_RM, MASK_FDIV_Q | MASK_RM, match_opcode, 0 },
560 {"fdiv.q", "Q", "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
|
| H A D | riscv-opc.h | 294 #define MATCH_FDIV_Q 0x1e000053 macro
918 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
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| /dports/lang/sdcc/sdcc-4.0.0/support/sdbinutils/include/opcode/ |
| H A D | riscv-opc.h | 296 #define MATCH_FDIV_Q 0x1e000053 macro
972 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
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| /dports/devel/binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 320 #define MATCH_FDIV_Q 0x1e000053 macro
1020 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
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| /dports/devel/arm-elf-binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 320 #define MATCH_FDIV_Q 0x1e000053 macro
1020 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
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| /dports/devel/gnulibiberty/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 320 #define MATCH_FDIV_Q 0x1e000053 macro
1020 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
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| /dports/devel/gdb/gdb-11.1/include/opcode/ |
| H A D | riscv-opc.h | 320 #define MATCH_FDIV_Q 0x1e000053 macro
1020 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
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| /dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
| H A D | riscv-opc.c | 662 {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opc…
663 {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
|
| /dports/devel/gdb/gdb-11.1/opcodes/ |
| H A D | riscv-opc.c | 662 {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opc…
663 {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
|
| /dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
| H A D | riscv-opc.c | 662 {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opc…
663 {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
|
| /dports/devel/binutils/binutils-2.37/opcodes/ |
| H A D | riscv-opc.c | 662 {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opc…
663 {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
|
| /dports/devel/openocd/openocd-0.11.0/src/target/riscv/ |
| H A D | encoding.h | 660 #define MATCH_FDIV_Q 0x1e000053 macro
2253 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
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| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
| H A D | encoding.h | 662 #define MATCH_FDIV_Q 0x1e000053 macro
3284 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
|